stm32f1/stm32f101/usb/
epr.rs

1///Register `EP%sR` reader
2pub type R = crate::R<EPRrs>;
3///Register `EP%sR` writer
4pub type W = crate::W<EPRrs>;
5///Field `EA` reader - Endpoint address
6pub type EA_R = crate::FieldReader;
7///Field `EA` writer - Endpoint address
8pub type EA_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
9/**Status bits, for transmission transfers
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14#[repr(u8)]
15pub enum STAT_TXR {
16    ///0: all transmission requests addressed to this endpoint are ignored
17    Disabled = 0,
18    ///1: the endpoint is stalled and all transmission requests result in a STALL handshake
19    Stall = 1,
20    ///2: the endpoint is naked and all transmission requests result in a NAK handshake
21    Nak = 2,
22    ///3: this endpoint is enabled for transmission
23    Valid = 3,
24}
25impl From<STAT_TXR> for u8 {
26    #[inline(always)]
27    fn from(variant: STAT_TXR) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for STAT_TXR {
32    type Ux = u8;
33}
34impl crate::IsEnum for STAT_TXR {}
35///Field `STAT_TX` reader - Status bits, for transmission transfers
36pub type STAT_TX_R = crate::FieldReader<STAT_TXR>;
37impl STAT_TX_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> STAT_TXR {
41        match self.bits {
42            0 => STAT_TXR::Disabled,
43            1 => STAT_TXR::Stall,
44            2 => STAT_TXR::Nak,
45            3 => STAT_TXR::Valid,
46            _ => unreachable!(),
47        }
48    }
49    ///all transmission requests addressed to this endpoint are ignored
50    #[inline(always)]
51    pub fn is_disabled(&self) -> bool {
52        *self == STAT_TXR::Disabled
53    }
54    ///the endpoint is stalled and all transmission requests result in a STALL handshake
55    #[inline(always)]
56    pub fn is_stall(&self) -> bool {
57        *self == STAT_TXR::Stall
58    }
59    ///the endpoint is naked and all transmission requests result in a NAK handshake
60    #[inline(always)]
61    pub fn is_nak(&self) -> bool {
62        *self == STAT_TXR::Nak
63    }
64    ///this endpoint is enabled for transmission
65    #[inline(always)]
66    pub fn is_valid(&self) -> bool {
67        *self == STAT_TXR::Valid
68    }
69}
70///Field `STAT_TX` writer - Status bits, for transmission transfers
71pub type STAT_TX_W<'a, REG> = crate::FieldWriter<'a, REG, 2, STAT_TXR, crate::Safe>;
72impl<'a, REG> STAT_TX_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    ///all transmission requests addressed to this endpoint are ignored
78    #[inline(always)]
79    pub fn disabled(self) -> &'a mut crate::W<REG> {
80        self.variant(STAT_TXR::Disabled)
81    }
82    ///the endpoint is stalled and all transmission requests result in a STALL handshake
83    #[inline(always)]
84    pub fn stall(self) -> &'a mut crate::W<REG> {
85        self.variant(STAT_TXR::Stall)
86    }
87    ///the endpoint is naked and all transmission requests result in a NAK handshake
88    #[inline(always)]
89    pub fn nak(self) -> &'a mut crate::W<REG> {
90        self.variant(STAT_TXR::Nak)
91    }
92    ///this endpoint is enabled for transmission
93    #[inline(always)]
94    pub fn valid(self) -> &'a mut crate::W<REG> {
95        self.variant(STAT_TXR::Valid)
96    }
97}
98///Field `DTOG_TX` reader - Data Toggle, for transmission transfers
99pub type DTOG_TX_R = crate::BitReader;
100///Field `DTOG_TX` writer - Data Toggle, for transmission transfers
101pub type DTOG_TX_W<'a, REG> = crate::BitWriter1T<'a, REG>;
102///Field `CTR_TX` reader - Correct Transfer for transmission
103pub type CTR_TX_R = crate::BitReader;
104///Field `CTR_TX` writer - Correct Transfer for transmission
105pub type CTR_TX_W<'a, REG> = crate::BitWriter0C<'a, REG>;
106///Field `EP_KIND` reader - Endpoint kind
107pub type EP_KIND_R = crate::BitReader;
108///Field `EP_KIND` writer - Endpoint kind
109pub type EP_KIND_W<'a, REG> = crate::BitWriter<'a, REG>;
110/**Endpoint type
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115#[repr(u8)]
116pub enum EP_TYPE {
117    ///0: Bulk endpoint
118    Bulk = 0,
119    ///1: Control endpoint
120    Control = 1,
121    ///2: Iso endpoint
122    Iso = 2,
123    ///3: Interrupt endpoint
124    Interrupt = 3,
125}
126impl From<EP_TYPE> for u8 {
127    #[inline(always)]
128    fn from(variant: EP_TYPE) -> Self {
129        variant as _
130    }
131}
132impl crate::FieldSpec for EP_TYPE {
133    type Ux = u8;
134}
135impl crate::IsEnum for EP_TYPE {}
136///Field `EP_TYPE` reader - Endpoint type
137pub type EP_TYPE_R = crate::FieldReader<EP_TYPE>;
138impl EP_TYPE_R {
139    ///Get enumerated values variant
140    #[inline(always)]
141    pub const fn variant(&self) -> EP_TYPE {
142        match self.bits {
143            0 => EP_TYPE::Bulk,
144            1 => EP_TYPE::Control,
145            2 => EP_TYPE::Iso,
146            3 => EP_TYPE::Interrupt,
147            _ => unreachable!(),
148        }
149    }
150    ///Bulk endpoint
151    #[inline(always)]
152    pub fn is_bulk(&self) -> bool {
153        *self == EP_TYPE::Bulk
154    }
155    ///Control endpoint
156    #[inline(always)]
157    pub fn is_control(&self) -> bool {
158        *self == EP_TYPE::Control
159    }
160    ///Iso endpoint
161    #[inline(always)]
162    pub fn is_iso(&self) -> bool {
163        *self == EP_TYPE::Iso
164    }
165    ///Interrupt endpoint
166    #[inline(always)]
167    pub fn is_interrupt(&self) -> bool {
168        *self == EP_TYPE::Interrupt
169    }
170}
171///Field `EP_TYPE` writer - Endpoint type
172pub type EP_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EP_TYPE, crate::Safe>;
173impl<'a, REG> EP_TYPE_W<'a, REG>
174where
175    REG: crate::Writable + crate::RegisterSpec,
176    REG::Ux: From<u8>,
177{
178    ///Bulk endpoint
179    #[inline(always)]
180    pub fn bulk(self) -> &'a mut crate::W<REG> {
181        self.variant(EP_TYPE::Bulk)
182    }
183    ///Control endpoint
184    #[inline(always)]
185    pub fn control(self) -> &'a mut crate::W<REG> {
186        self.variant(EP_TYPE::Control)
187    }
188    ///Iso endpoint
189    #[inline(always)]
190    pub fn iso(self) -> &'a mut crate::W<REG> {
191        self.variant(EP_TYPE::Iso)
192    }
193    ///Interrupt endpoint
194    #[inline(always)]
195    pub fn interrupt(self) -> &'a mut crate::W<REG> {
196        self.variant(EP_TYPE::Interrupt)
197    }
198}
199///Field `SETUP` reader - Setup transaction completed
200pub type SETUP_R = crate::BitReader;
201///Field `SETUP` writer - Setup transaction completed
202pub type SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
203/**Status bits, for reception transfers
204
205Value on reset: 0*/
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208#[repr(u8)]
209pub enum STAT_RXR {
210    ///0: all reception requests addressed to this endpoint are ignored
211    Disabled = 0,
212    ///1: the endpoint is stalled and all reception requests result in a STALL handshake
213    Stall = 1,
214    ///2: the endpoint is naked and all reception requests result in a NAK handshake
215    Nak = 2,
216    ///3: this endpoint is enabled for reception
217    Valid = 3,
218}
219impl From<STAT_RXR> for u8 {
220    #[inline(always)]
221    fn from(variant: STAT_RXR) -> Self {
222        variant as _
223    }
224}
225impl crate::FieldSpec for STAT_RXR {
226    type Ux = u8;
227}
228impl crate::IsEnum for STAT_RXR {}
229///Field `STAT_RX` reader - Status bits, for reception transfers
230pub type STAT_RX_R = crate::FieldReader<STAT_RXR>;
231impl STAT_RX_R {
232    ///Get enumerated values variant
233    #[inline(always)]
234    pub const fn variant(&self) -> STAT_RXR {
235        match self.bits {
236            0 => STAT_RXR::Disabled,
237            1 => STAT_RXR::Stall,
238            2 => STAT_RXR::Nak,
239            3 => STAT_RXR::Valid,
240            _ => unreachable!(),
241        }
242    }
243    ///all reception requests addressed to this endpoint are ignored
244    #[inline(always)]
245    pub fn is_disabled(&self) -> bool {
246        *self == STAT_RXR::Disabled
247    }
248    ///the endpoint is stalled and all reception requests result in a STALL handshake
249    #[inline(always)]
250    pub fn is_stall(&self) -> bool {
251        *self == STAT_RXR::Stall
252    }
253    ///the endpoint is naked and all reception requests result in a NAK handshake
254    #[inline(always)]
255    pub fn is_nak(&self) -> bool {
256        *self == STAT_RXR::Nak
257    }
258    ///this endpoint is enabled for reception
259    #[inline(always)]
260    pub fn is_valid(&self) -> bool {
261        *self == STAT_RXR::Valid
262    }
263}
264///Field `STAT_RX` writer - Status bits, for reception transfers
265pub type STAT_RX_W<'a, REG> = crate::FieldWriter<'a, REG, 2, STAT_RXR, crate::Safe>;
266impl<'a, REG> STAT_RX_W<'a, REG>
267where
268    REG: crate::Writable + crate::RegisterSpec,
269    REG::Ux: From<u8>,
270{
271    ///all reception requests addressed to this endpoint are ignored
272    #[inline(always)]
273    pub fn disabled(self) -> &'a mut crate::W<REG> {
274        self.variant(STAT_RXR::Disabled)
275    }
276    ///the endpoint is stalled and all reception requests result in a STALL handshake
277    #[inline(always)]
278    pub fn stall(self) -> &'a mut crate::W<REG> {
279        self.variant(STAT_RXR::Stall)
280    }
281    ///the endpoint is naked and all reception requests result in a NAK handshake
282    #[inline(always)]
283    pub fn nak(self) -> &'a mut crate::W<REG> {
284        self.variant(STAT_RXR::Nak)
285    }
286    ///this endpoint is enabled for reception
287    #[inline(always)]
288    pub fn valid(self) -> &'a mut crate::W<REG> {
289        self.variant(STAT_RXR::Valid)
290    }
291}
292///Field `DTOG_RX` reader - Data Toggle, for reception transfers
293pub type DTOG_RX_R = crate::BitReader;
294///Field `DTOG_RX` writer - Data Toggle, for reception transfers
295pub type DTOG_RX_W<'a, REG> = crate::BitWriter1T<'a, REG>;
296///Field `CTR_RX` reader - Correct transfer for reception
297pub type CTR_RX_R = crate::BitReader;
298///Field `CTR_RX` writer - Correct transfer for reception
299pub type CTR_RX_W<'a, REG> = crate::BitWriter0C<'a, REG>;
300impl R {
301    ///Bits 0:3 - Endpoint address
302    #[inline(always)]
303    pub fn ea(&self) -> EA_R {
304        EA_R::new((self.bits & 0x0f) as u8)
305    }
306    ///Bits 4:5 - Status bits, for transmission transfers
307    #[inline(always)]
308    pub fn stat_tx(&self) -> STAT_TX_R {
309        STAT_TX_R::new(((self.bits >> 4) & 3) as u8)
310    }
311    ///Bit 6 - Data Toggle, for transmission transfers
312    #[inline(always)]
313    pub fn dtog_tx(&self) -> DTOG_TX_R {
314        DTOG_TX_R::new(((self.bits >> 6) & 1) != 0)
315    }
316    ///Bit 7 - Correct Transfer for transmission
317    #[inline(always)]
318    pub fn ctr_tx(&self) -> CTR_TX_R {
319        CTR_TX_R::new(((self.bits >> 7) & 1) != 0)
320    }
321    ///Bit 8 - Endpoint kind
322    #[inline(always)]
323    pub fn ep_kind(&self) -> EP_KIND_R {
324        EP_KIND_R::new(((self.bits >> 8) & 1) != 0)
325    }
326    ///Bits 9:10 - Endpoint type
327    #[inline(always)]
328    pub fn ep_type(&self) -> EP_TYPE_R {
329        EP_TYPE_R::new(((self.bits >> 9) & 3) as u8)
330    }
331    ///Bit 11 - Setup transaction completed
332    #[inline(always)]
333    pub fn setup(&self) -> SETUP_R {
334        SETUP_R::new(((self.bits >> 11) & 1) != 0)
335    }
336    ///Bits 12:13 - Status bits, for reception transfers
337    #[inline(always)]
338    pub fn stat_rx(&self) -> STAT_RX_R {
339        STAT_RX_R::new(((self.bits >> 12) & 3) as u8)
340    }
341    ///Bit 14 - Data Toggle, for reception transfers
342    #[inline(always)]
343    pub fn dtog_rx(&self) -> DTOG_RX_R {
344        DTOG_RX_R::new(((self.bits >> 14) & 1) != 0)
345    }
346    ///Bit 15 - Correct transfer for reception
347    #[inline(always)]
348    pub fn ctr_rx(&self) -> CTR_RX_R {
349        CTR_RX_R::new(((self.bits >> 15) & 1) != 0)
350    }
351}
352impl core::fmt::Debug for R {
353    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
354        f.debug_struct("EPR")
355            .field("ea", &self.ea())
356            .field("stat_tx", &self.stat_tx())
357            .field("dtog_tx", &self.dtog_tx())
358            .field("ctr_tx", &self.ctr_tx())
359            .field("ep_kind", &self.ep_kind())
360            .field("ep_type", &self.ep_type())
361            .field("setup", &self.setup())
362            .field("stat_rx", &self.stat_rx())
363            .field("dtog_rx", &self.dtog_rx())
364            .field("ctr_rx", &self.ctr_rx())
365            .finish()
366    }
367}
368impl W {
369    ///Bits 0:3 - Endpoint address
370    #[inline(always)]
371    pub fn ea(&mut self) -> EA_W<EPRrs> {
372        EA_W::new(self, 0)
373    }
374    ///Bits 4:5 - Status bits, for transmission transfers
375    #[inline(always)]
376    pub fn stat_tx(&mut self) -> STAT_TX_W<EPRrs> {
377        STAT_TX_W::new(self, 4)
378    }
379    ///Bit 6 - Data Toggle, for transmission transfers
380    #[inline(always)]
381    pub fn dtog_tx(&mut self) -> DTOG_TX_W<EPRrs> {
382        DTOG_TX_W::new(self, 6)
383    }
384    ///Bit 7 - Correct Transfer for transmission
385    #[inline(always)]
386    pub fn ctr_tx(&mut self) -> CTR_TX_W<EPRrs> {
387        CTR_TX_W::new(self, 7)
388    }
389    ///Bit 8 - Endpoint kind
390    #[inline(always)]
391    pub fn ep_kind(&mut self) -> EP_KIND_W<EPRrs> {
392        EP_KIND_W::new(self, 8)
393    }
394    ///Bits 9:10 - Endpoint type
395    #[inline(always)]
396    pub fn ep_type(&mut self) -> EP_TYPE_W<EPRrs> {
397        EP_TYPE_W::new(self, 9)
398    }
399    ///Bit 11 - Setup transaction completed
400    #[inline(always)]
401    pub fn setup(&mut self) -> SETUP_W<EPRrs> {
402        SETUP_W::new(self, 11)
403    }
404    ///Bits 12:13 - Status bits, for reception transfers
405    #[inline(always)]
406    pub fn stat_rx(&mut self) -> STAT_RX_W<EPRrs> {
407        STAT_RX_W::new(self, 12)
408    }
409    ///Bit 14 - Data Toggle, for reception transfers
410    #[inline(always)]
411    pub fn dtog_rx(&mut self) -> DTOG_RX_W<EPRrs> {
412        DTOG_RX_W::new(self, 14)
413    }
414    ///Bit 15 - Correct transfer for reception
415    #[inline(always)]
416    pub fn ctr_rx(&mut self) -> CTR_RX_W<EPRrs> {
417        CTR_RX_W::new(self, 15)
418    }
419}
420/**endpoint %s register
421
422You can [`read`](crate::Reg::read) this register and get [`epr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`epr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
423
424See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#USB:EP[0]R)*/
425pub struct EPRrs;
426impl crate::RegisterSpec for EPRrs {
427    type Ux = u32;
428}
429///`read()` method returns [`epr::R`](R) reader structure
430impl crate::Readable for EPRrs {}
431///`write(|w| ..)` method takes [`epr::W`](W) writer structure
432impl crate::Writable for EPRrs {
433    type Safety = crate::Unsafe;
434    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8080;
435    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x7070;
436}
437///`reset()` method sets EP%sR to value 0
438impl crate::Resettable for EPRrs {}
stm32f1/stm32f101/usb/epr.rs

stm32f1/stm32f101/usb/
epr.rs
