stm32f1/stm32f101/tim9/
dier.rs

1///Register `DIER` reader
2pub type R = crate::R<DIERrs>;
3///Register `DIER` writer
4pub type W = crate::W<DIERrs>;
5/**Update interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIE {
11    ///0: Update interrupt disabled
12    Disabled = 0,
13    ///1: Update interrupt enabled
14    Enabled = 1,
15}
16impl From<UIE> for bool {
17    #[inline(always)]
18    fn from(variant: UIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIE` reader - Update interrupt enable
23pub type UIE_R = crate::BitReader<UIE>;
24impl UIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIE {
28        match self.bits {
29            false => UIE::Disabled,
30            true => UIE::Enabled,
31        }
32    }
33    ///Update interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == UIE::Disabled
37    }
38    ///Update interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == UIE::Enabled
42    }
43}
44///Field `UIE` writer - Update interrupt enable
45pub type UIE_W<'a, REG> = crate::BitWriter<'a, REG, UIE>;
46impl<'a, REG> UIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Update interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(UIE::Disabled)
54    }
55    ///Update interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(UIE::Enabled)
59    }
60}
61/**Capture/Compare %s interrupt enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1IE {
67    ///0: CCx interrupt disabled
68    Disabled = 0,
69    ///1: CCx interrupt enabled
70    Enabled = 1,
71}
72impl From<CC1IE> for bool {
73    #[inline(always)]
74    fn from(variant: CC1IE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCIE(1-2)` reader - Capture/Compare %s interrupt enable
79pub type CCIE_R = crate::BitReader<CC1IE>;
80impl CCIE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1IE {
84        match self.bits {
85            false => CC1IE::Disabled,
86            true => CC1IE::Enabled,
87        }
88    }
89    ///CCx interrupt disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == CC1IE::Disabled
93    }
94    ///CCx interrupt enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == CC1IE::Enabled
98    }
99}
100///Field `CCIE(1-2)` writer - Capture/Compare %s interrupt enable
101pub type CCIE_W<'a, REG> = crate::BitWriter<'a, REG, CC1IE>;
102impl<'a, REG> CCIE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///CCx interrupt disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1IE::Disabled)
110    }
111    ///CCx interrupt enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1IE::Enabled)
115    }
116}
117/**Trigger interrupt enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum TIE {
123    ///0: Trigger interrupt disabled
124    Disabled = 0,
125    ///1: Trigger interrupt enabled
126    Enabled = 1,
127}
128impl From<TIE> for bool {
129    #[inline(always)]
130    fn from(variant: TIE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `TIE` reader - Trigger interrupt enable
135pub type TIE_R = crate::BitReader<TIE>;
136impl TIE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> TIE {
140        match self.bits {
141            false => TIE::Disabled,
142            true => TIE::Enabled,
143        }
144    }
145    ///Trigger interrupt disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == TIE::Disabled
149    }
150    ///Trigger interrupt enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == TIE::Enabled
154    }
155}
156///Field `TIE` writer - Trigger interrupt enable
157pub type TIE_W<'a, REG> = crate::BitWriter<'a, REG, TIE>;
158impl<'a, REG> TIE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Trigger interrupt disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(TIE::Disabled)
166    }
167    ///Trigger interrupt enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(TIE::Enabled)
171    }
172}
173impl R {
174    ///Bit 0 - Update interrupt enable
175    #[inline(always)]
176    pub fn uie(&self) -> UIE_R {
177        UIE_R::new((self.bits & 1) != 0)
178    }
179    ///Capture/Compare (1-2) interrupt enable
180    ///
181    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
182    #[inline(always)]
183    pub fn ccie(&self, n: u8) -> CCIE_R {
184        #[allow(clippy::no_effect)]
185        [(); 2][n as usize];
186        CCIE_R::new(((self.bits >> (n + 1)) & 1) != 0)
187    }
188    ///Iterator for array of:
189    ///Capture/Compare (1-2) interrupt enable
190    #[inline(always)]
191    pub fn ccie_iter(&self) -> impl Iterator<Item = CCIE_R> + '_ {
192        (0..2).map(move |n| CCIE_R::new(((self.bits >> (n + 1)) & 1) != 0))
193    }
194    ///Bit 1 - Capture/Compare 1 interrupt enable
195    #[inline(always)]
196    pub fn cc1ie(&self) -> CCIE_R {
197        CCIE_R::new(((self.bits >> 1) & 1) != 0)
198    }
199    ///Bit 2 - Capture/Compare 2 interrupt enable
200    #[inline(always)]
201    pub fn cc2ie(&self) -> CCIE_R {
202        CCIE_R::new(((self.bits >> 2) & 1) != 0)
203    }
204    ///Bit 6 - Trigger interrupt enable
205    #[inline(always)]
206    pub fn tie(&self) -> TIE_R {
207        TIE_R::new(((self.bits >> 6) & 1) != 0)
208    }
209}
210impl core::fmt::Debug for R {
211    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
212        f.debug_struct("DIER")
213            .field("tie", &self.tie())
214            .field("cc1ie", &self.cc1ie())
215            .field("cc2ie", &self.cc2ie())
216            .field("uie", &self.uie())
217            .finish()
218    }
219}
220impl W {
221    ///Bit 0 - Update interrupt enable
222    #[inline(always)]
223    pub fn uie(&mut self) -> UIE_W<DIERrs> {
224        UIE_W::new(self, 0)
225    }
226    ///Capture/Compare (1-2) interrupt enable
227    ///
228    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
229    #[inline(always)]
230    pub fn ccie(&mut self, n: u8) -> CCIE_W<DIERrs> {
231        #[allow(clippy::no_effect)]
232        [(); 2][n as usize];
233        CCIE_W::new(self, n + 1)
234    }
235    ///Bit 1 - Capture/Compare 1 interrupt enable
236    #[inline(always)]
237    pub fn cc1ie(&mut self) -> CCIE_W<DIERrs> {
238        CCIE_W::new(self, 1)
239    }
240    ///Bit 2 - Capture/Compare 2 interrupt enable
241    #[inline(always)]
242    pub fn cc2ie(&mut self) -> CCIE_W<DIERrs> {
243        CCIE_W::new(self, 2)
244    }
245    ///Bit 6 - Trigger interrupt enable
246    #[inline(always)]
247    pub fn tie(&mut self) -> TIE_W<DIERrs> {
248        TIE_W::new(self, 6)
249    }
250}
251/**DMA/Interrupt enable register
252
253You can [`read`](crate::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
254
255See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM9:DIER)*/
256pub struct DIERrs;
257impl crate::RegisterSpec for DIERrs {
258    type Ux = u32;
259}
260///`read()` method returns [`dier::R`](R) reader structure
261impl crate::Readable for DIERrs {}
262///`write(|w| ..)` method takes [`dier::W`](W) writer structure
263impl crate::Writable for DIERrs {
264    type Safety = crate::Unsafe;
265}
266///`reset()` method sets DIER to value 0
267impl crate::Resettable for DIERrs {}
stm32f1/stm32f101/tim9/dier.rs

stm32f1/stm32f101/tim9/
dier.rs
