stm32f1/stm32f101/tim6/
dier.rs

1///Register `DIER` reader
2pub type R = crate::R<DIERrs>;
3///Register `DIER` writer
4pub type W = crate::W<DIERrs>;
5/**Update interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIE {
11    ///0: Update interrupt disabled
12    Disabled = 0,
13    ///1: Update interrupt enabled
14    Enabled = 1,
15}
16impl From<UIE> for bool {
17    #[inline(always)]
18    fn from(variant: UIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIE` reader - Update interrupt enable
23pub type UIE_R = crate::BitReader<UIE>;
24impl UIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIE {
28        match self.bits {
29            false => UIE::Disabled,
30            true => UIE::Enabled,
31        }
32    }
33    ///Update interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == UIE::Disabled
37    }
38    ///Update interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == UIE::Enabled
42    }
43}
44///Field `UIE` writer - Update interrupt enable
45pub type UIE_W<'a, REG> = crate::BitWriter<'a, REG, UIE>;
46impl<'a, REG> UIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Update interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(UIE::Disabled)
54    }
55    ///Update interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(UIE::Enabled)
59    }
60}
61/**Update DMA request enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum UDE {
67    ///0: Update DMA request disabled
68    Disabled = 0,
69    ///1: Update DMA request enabled
70    Enabled = 1,
71}
72impl From<UDE> for bool {
73    #[inline(always)]
74    fn from(variant: UDE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `UDE` reader - Update DMA request enable
79pub type UDE_R = crate::BitReader<UDE>;
80impl UDE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> UDE {
84        match self.bits {
85            false => UDE::Disabled,
86            true => UDE::Enabled,
87        }
88    }
89    ///Update DMA request disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == UDE::Disabled
93    }
94    ///Update DMA request enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == UDE::Enabled
98    }
99}
100///Field `UDE` writer - Update DMA request enable
101pub type UDE_W<'a, REG> = crate::BitWriter<'a, REG, UDE>;
102impl<'a, REG> UDE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Update DMA request disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(UDE::Disabled)
110    }
111    ///Update DMA request enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(UDE::Enabled)
115    }
116}
117impl R {
118    ///Bit 0 - Update interrupt enable
119    #[inline(always)]
120    pub fn uie(&self) -> UIE_R {
121        UIE_R::new((self.bits & 1) != 0)
122    }
123    ///Bit 8 - Update DMA request enable
124    #[inline(always)]
125    pub fn ude(&self) -> UDE_R {
126        UDE_R::new(((self.bits >> 8) & 1) != 0)
127    }
128}
129impl core::fmt::Debug for R {
130    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
131        f.debug_struct("DIER")
132            .field("ude", &self.ude())
133            .field("uie", &self.uie())
134            .finish()
135    }
136}
137impl W {
138    ///Bit 0 - Update interrupt enable
139    #[inline(always)]
140    pub fn uie(&mut self) -> UIE_W<DIERrs> {
141        UIE_W::new(self, 0)
142    }
143    ///Bit 8 - Update DMA request enable
144    #[inline(always)]
145    pub fn ude(&mut self) -> UDE_W<DIERrs> {
146        UDE_W::new(self, 8)
147    }
148}
149/**DMA/Interrupt enable register
150
151You can [`read`](crate::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
152
153See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:DIER)*/
154pub struct DIERrs;
155impl crate::RegisterSpec for DIERrs {
156    type Ux = u32;
157}
158///`read()` method returns [`dier::R`](R) reader structure
159impl crate::Readable for DIERrs {}
160///`write(|w| ..)` method takes [`dier::W`](W) writer structure
161impl crate::Writable for DIERrs {
162    type Safety = crate::Unsafe;
163}
164///`reset()` method sets DIER to value 0
165impl crate::Resettable for DIERrs {}
stm32f1/stm32f101/tim6/dier.rs

stm32f1/stm32f101/tim6/
dier.rs
