stm32f1/stm32f101/adc1/
dr.rs

1///Register `DR` reader
2pub type R = crate::R<DRrs>;
3///Field `DATA` reader - Regular data
4pub type DATA_R = crate::FieldReader<u16>;
5///Field `ADC2DATA` reader - ADC2 data
6pub type ADC2DATA_R = crate::FieldReader<u16>;
7impl R {
8    ///Bits 0:15 - Regular data
9    #[inline(always)]
10    pub fn data(&self) -> DATA_R {
11        DATA_R::new((self.bits & 0xffff) as u16)
12    }
13    ///Bits 16:31 - ADC2 data
14    #[inline(always)]
15    pub fn adc2data(&self) -> ADC2DATA_R {
16        ADC2DATA_R::new(((self.bits >> 16) & 0xffff) as u16)
17    }
18}
19impl core::fmt::Debug for R {
20    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21        f.debug_struct("DR")
22            .field("data", &self.data())
23            .field("adc2data", &self.adc2data())
24            .finish()
25    }
26}
27/**regular data register
28
29You can [`read`](crate::Reg::read) this register and get [`dr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
30
31See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#ADC1:DR)*/
32pub struct DRrs;
33impl crate::RegisterSpec for DRrs {
34    type Ux = u32;
35}
36///`read()` method returns [`dr::R`](R) reader structure
37impl crate::Readable for DRrs {}
38///`reset()` method sets DR to value 0
39impl crate::Resettable for DRrs {}
stm32f1/stm32f101/adc1/dr.rs

stm32f1/stm32f101/adc1/
dr.rs
