stm32f1/stm32f100/tim2/
smcr.rs

1///Register `SMCR` reader
2pub type R = crate::R<SMCRrs>;
3///Register `SMCR` writer
4pub type W = crate::W<SMCRrs>;
5/**Slave mode selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum SMS {
12    ///0: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
13    Disabled = 0,
14    ///1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
15    EncoderMode1 = 1,
16    ///2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
17    EncoderMode2 = 2,
18    ///3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
19    EncoderMode3 = 3,
20    ///4: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
21    ResetMode = 4,
22    ///5: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
23    GatedMode = 5,
24    ///6: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
25    TriggerMode = 6,
26    ///7: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
27    ExtClockMode = 7,
28}
29impl From<SMS> for u8 {
30    #[inline(always)]
31    fn from(variant: SMS) -> Self {
32        variant as _
33    }
34}
35impl crate::FieldSpec for SMS {
36    type Ux = u8;
37}
38impl crate::IsEnum for SMS {}
39///Field `SMS` reader - Slave mode selection
40pub type SMS_R = crate::FieldReader<SMS>;
41impl SMS_R {
42    ///Get enumerated values variant
43    #[inline(always)]
44    pub const fn variant(&self) -> SMS {
45        match self.bits {
46            0 => SMS::Disabled,
47            1 => SMS::EncoderMode1,
48            2 => SMS::EncoderMode2,
49            3 => SMS::EncoderMode3,
50            4 => SMS::ResetMode,
51            5 => SMS::GatedMode,
52            6 => SMS::TriggerMode,
53            7 => SMS::ExtClockMode,
54            _ => unreachable!(),
55        }
56    }
57    ///Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
58    #[inline(always)]
59    pub fn is_disabled(&self) -> bool {
60        *self == SMS::Disabled
61    }
62    ///Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
63    #[inline(always)]
64    pub fn is_encoder_mode_1(&self) -> bool {
65        *self == SMS::EncoderMode1
66    }
67    ///Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
68    #[inline(always)]
69    pub fn is_encoder_mode_2(&self) -> bool {
70        *self == SMS::EncoderMode2
71    }
72    ///Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
73    #[inline(always)]
74    pub fn is_encoder_mode_3(&self) -> bool {
75        *self == SMS::EncoderMode3
76    }
77    ///Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
78    #[inline(always)]
79    pub fn is_reset_mode(&self) -> bool {
80        *self == SMS::ResetMode
81    }
82    ///Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
83    #[inline(always)]
84    pub fn is_gated_mode(&self) -> bool {
85        *self == SMS::GatedMode
86    }
87    ///Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
88    #[inline(always)]
89    pub fn is_trigger_mode(&self) -> bool {
90        *self == SMS::TriggerMode
91    }
92    ///External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
93    #[inline(always)]
94    pub fn is_ext_clock_mode(&self) -> bool {
95        *self == SMS::ExtClockMode
96    }
97}
98///Field `SMS` writer - Slave mode selection
99pub type SMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SMS, crate::Safe>;
100impl<'a, REG> SMS_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103    REG::Ux: From<u8>,
104{
105    ///Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
106    #[inline(always)]
107    pub fn disabled(self) -> &'a mut crate::W<REG> {
108        self.variant(SMS::Disabled)
109    }
110    ///Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
111    #[inline(always)]
112    pub fn encoder_mode_1(self) -> &'a mut crate::W<REG> {
113        self.variant(SMS::EncoderMode1)
114    }
115    ///Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
116    #[inline(always)]
117    pub fn encoder_mode_2(self) -> &'a mut crate::W<REG> {
118        self.variant(SMS::EncoderMode2)
119    }
120    ///Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
121    #[inline(always)]
122    pub fn encoder_mode_3(self) -> &'a mut crate::W<REG> {
123        self.variant(SMS::EncoderMode3)
124    }
125    ///Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
126    #[inline(always)]
127    pub fn reset_mode(self) -> &'a mut crate::W<REG> {
128        self.variant(SMS::ResetMode)
129    }
130    ///Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
131    #[inline(always)]
132    pub fn gated_mode(self) -> &'a mut crate::W<REG> {
133        self.variant(SMS::GatedMode)
134    }
135    ///Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
136    #[inline(always)]
137    pub fn trigger_mode(self) -> &'a mut crate::W<REG> {
138        self.variant(SMS::TriggerMode)
139    }
140    ///External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
141    #[inline(always)]
142    pub fn ext_clock_mode(self) -> &'a mut crate::W<REG> {
143        self.variant(SMS::ExtClockMode)
144    }
145}
146///Field `OCCS` reader - OCREF clear selection
147pub type OCCS_R = crate::BitReader;
148///Field `OCCS` writer - OCREF clear selection
149pub type OCCS_W<'a, REG> = crate::BitWriter<'a, REG>;
150/**Trigger selection
151
152Value on reset: 0*/
153#[cfg_attr(feature = "defmt", derive(defmt::Format))]
154#[derive(Clone, Copy, Debug, PartialEq, Eq)]
155#[repr(u8)]
156pub enum TS {
157    ///0: Internal Trigger 0 (ITR0)
158    Itr0 = 0,
159    ///1: Internal Trigger 1 (ITR1)
160    Itr1 = 1,
161    ///2: Internal Trigger 2 (ITR2)
162    Itr2 = 2,
163    ///4: TI1 Edge Detector (TI1F_ED)
164    Ti1fEd = 4,
165    ///5: Filtered Timer Input 1 (TI1FP1)
166    Ti1fp1 = 5,
167    ///6: Filtered Timer Input 2 (TI2FP2)
168    Ti2fp2 = 6,
169    ///7: External Trigger input (ETRF)
170    Etrf = 7,
171}
172impl From<TS> for u8 {
173    #[inline(always)]
174    fn from(variant: TS) -> Self {
175        variant as _
176    }
177}
178impl crate::FieldSpec for TS {
179    type Ux = u8;
180}
181impl crate::IsEnum for TS {}
182///Field `TS` reader - Trigger selection
183pub type TS_R = crate::FieldReader<TS>;
184impl TS_R {
185    ///Get enumerated values variant
186    #[inline(always)]
187    pub const fn variant(&self) -> Option<TS> {
188        match self.bits {
189            0 => Some(TS::Itr0),
190            1 => Some(TS::Itr1),
191            2 => Some(TS::Itr2),
192            4 => Some(TS::Ti1fEd),
193            5 => Some(TS::Ti1fp1),
194            6 => Some(TS::Ti2fp2),
195            7 => Some(TS::Etrf),
196            _ => None,
197        }
198    }
199    ///Internal Trigger 0 (ITR0)
200    #[inline(always)]
201    pub fn is_itr0(&self) -> bool {
202        *self == TS::Itr0
203    }
204    ///Internal Trigger 1 (ITR1)
205    #[inline(always)]
206    pub fn is_itr1(&self) -> bool {
207        *self == TS::Itr1
208    }
209    ///Internal Trigger 2 (ITR2)
210    #[inline(always)]
211    pub fn is_itr2(&self) -> bool {
212        *self == TS::Itr2
213    }
214    ///TI1 Edge Detector (TI1F_ED)
215    #[inline(always)]
216    pub fn is_ti1f_ed(&self) -> bool {
217        *self == TS::Ti1fEd
218    }
219    ///Filtered Timer Input 1 (TI1FP1)
220    #[inline(always)]
221    pub fn is_ti1fp1(&self) -> bool {
222        *self == TS::Ti1fp1
223    }
224    ///Filtered Timer Input 2 (TI2FP2)
225    #[inline(always)]
226    pub fn is_ti2fp2(&self) -> bool {
227        *self == TS::Ti2fp2
228    }
229    ///External Trigger input (ETRF)
230    #[inline(always)]
231    pub fn is_etrf(&self) -> bool {
232        *self == TS::Etrf
233    }
234}
235///Field `TS` writer - Trigger selection
236pub type TS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TS>;
237impl<'a, REG> TS_W<'a, REG>
238where
239    REG: crate::Writable + crate::RegisterSpec,
240    REG::Ux: From<u8>,
241{
242    ///Internal Trigger 0 (ITR0)
243    #[inline(always)]
244    pub fn itr0(self) -> &'a mut crate::W<REG> {
245        self.variant(TS::Itr0)
246    }
247    ///Internal Trigger 1 (ITR1)
248    #[inline(always)]
249    pub fn itr1(self) -> &'a mut crate::W<REG> {
250        self.variant(TS::Itr1)
251    }
252    ///Internal Trigger 2 (ITR2)
253    #[inline(always)]
254    pub fn itr2(self) -> &'a mut crate::W<REG> {
255        self.variant(TS::Itr2)
256    }
257    ///TI1 Edge Detector (TI1F_ED)
258    #[inline(always)]
259    pub fn ti1f_ed(self) -> &'a mut crate::W<REG> {
260        self.variant(TS::Ti1fEd)
261    }
262    ///Filtered Timer Input 1 (TI1FP1)
263    #[inline(always)]
264    pub fn ti1fp1(self) -> &'a mut crate::W<REG> {
265        self.variant(TS::Ti1fp1)
266    }
267    ///Filtered Timer Input 2 (TI2FP2)
268    #[inline(always)]
269    pub fn ti2fp2(self) -> &'a mut crate::W<REG> {
270        self.variant(TS::Ti2fp2)
271    }
272    ///External Trigger input (ETRF)
273    #[inline(always)]
274    pub fn etrf(self) -> &'a mut crate::W<REG> {
275        self.variant(TS::Etrf)
276    }
277}
278/**Master/Slave mode
279
280Value on reset: 0*/
281#[cfg_attr(feature = "defmt", derive(defmt::Format))]
282#[derive(Clone, Copy, Debug, PartialEq, Eq)]
283pub enum MSM {
284    ///0: No action
285    NoSync = 0,
286    ///1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
287    Sync = 1,
288}
289impl From<MSM> for bool {
290    #[inline(always)]
291    fn from(variant: MSM) -> Self {
292        variant as u8 != 0
293    }
294}
295///Field `MSM` reader - Master/Slave mode
296pub type MSM_R = crate::BitReader<MSM>;
297impl MSM_R {
298    ///Get enumerated values variant
299    #[inline(always)]
300    pub const fn variant(&self) -> MSM {
301        match self.bits {
302            false => MSM::NoSync,
303            true => MSM::Sync,
304        }
305    }
306    ///No action
307    #[inline(always)]
308    pub fn is_no_sync(&self) -> bool {
309        *self == MSM::NoSync
310    }
311    ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
312    #[inline(always)]
313    pub fn is_sync(&self) -> bool {
314        *self == MSM::Sync
315    }
316}
317///Field `MSM` writer - Master/Slave mode
318pub type MSM_W<'a, REG> = crate::BitWriter<'a, REG, MSM>;
319impl<'a, REG> MSM_W<'a, REG>
320where
321    REG: crate::Writable + crate::RegisterSpec,
322{
323    ///No action
324    #[inline(always)]
325    pub fn no_sync(self) -> &'a mut crate::W<REG> {
326        self.variant(MSM::NoSync)
327    }
328    ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
329    #[inline(always)]
330    pub fn sync(self) -> &'a mut crate::W<REG> {
331        self.variant(MSM::Sync)
332    }
333}
334/**External trigger filter
335
336Value on reset: 0*/
337#[cfg_attr(feature = "defmt", derive(defmt::Format))]
338#[derive(Clone, Copy, Debug, PartialEq, Eq)]
339#[repr(u8)]
340pub enum ETF {
341    ///0: No filter, sampling is done at fDTS
342    NoFilter = 0,
343    ///1: fSAMPLING=fCK_INT, N=2
344    FckIntN2 = 1,
345    ///2: fSAMPLING=fCK_INT, N=4
346    FckIntN4 = 2,
347    ///3: fSAMPLING=fCK_INT, N=8
348    FckIntN8 = 3,
349    ///4: fSAMPLING=fDTS/2, N=6
350    FdtsDiv2N6 = 4,
351    ///5: fSAMPLING=fDTS/2, N=8
352    FdtsDiv2N8 = 5,
353    ///6: fSAMPLING=fDTS/4, N=6
354    FdtsDiv4N6 = 6,
355    ///7: fSAMPLING=fDTS/4, N=8
356    FdtsDiv4N8 = 7,
357    ///8: fSAMPLING=fDTS/8, N=6
358    FdtsDiv8N6 = 8,
359    ///9: fSAMPLING=fDTS/8, N=8
360    FdtsDiv8N8 = 9,
361    ///10: fSAMPLING=fDTS/16, N=5
362    FdtsDiv16N5 = 10,
363    ///11: fSAMPLING=fDTS/16, N=6
364    FdtsDiv16N6 = 11,
365    ///12: fSAMPLING=fDTS/16, N=8
366    FdtsDiv16N8 = 12,
367    ///13: fSAMPLING=fDTS/32, N=5
368    FdtsDiv32N5 = 13,
369    ///14: fSAMPLING=fDTS/32, N=6
370    FdtsDiv32N6 = 14,
371    ///15: fSAMPLING=fDTS/32, N=8
372    FdtsDiv32N8 = 15,
373}
374impl From<ETF> for u8 {
375    #[inline(always)]
376    fn from(variant: ETF) -> Self {
377        variant as _
378    }
379}
380impl crate::FieldSpec for ETF {
381    type Ux = u8;
382}
383impl crate::IsEnum for ETF {}
384///Field `ETF` reader - External trigger filter
385pub type ETF_R = crate::FieldReader<ETF>;
386impl ETF_R {
387    ///Get enumerated values variant
388    #[inline(always)]
389    pub const fn variant(&self) -> ETF {
390        match self.bits {
391            0 => ETF::NoFilter,
392            1 => ETF::FckIntN2,
393            2 => ETF::FckIntN4,
394            3 => ETF::FckIntN8,
395            4 => ETF::FdtsDiv2N6,
396            5 => ETF::FdtsDiv2N8,
397            6 => ETF::FdtsDiv4N6,
398            7 => ETF::FdtsDiv4N8,
399            8 => ETF::FdtsDiv8N6,
400            9 => ETF::FdtsDiv8N8,
401            10 => ETF::FdtsDiv16N5,
402            11 => ETF::FdtsDiv16N6,
403            12 => ETF::FdtsDiv16N8,
404            13 => ETF::FdtsDiv32N5,
405            14 => ETF::FdtsDiv32N6,
406            15 => ETF::FdtsDiv32N8,
407            _ => unreachable!(),
408        }
409    }
410    ///No filter, sampling is done at fDTS
411    #[inline(always)]
412    pub fn is_no_filter(&self) -> bool {
413        *self == ETF::NoFilter
414    }
415    ///fSAMPLING=fCK_INT, N=2
416    #[inline(always)]
417    pub fn is_fck_int_n2(&self) -> bool {
418        *self == ETF::FckIntN2
419    }
420    ///fSAMPLING=fCK_INT, N=4
421    #[inline(always)]
422    pub fn is_fck_int_n4(&self) -> bool {
423        *self == ETF::FckIntN4
424    }
425    ///fSAMPLING=fCK_INT, N=8
426    #[inline(always)]
427    pub fn is_fck_int_n8(&self) -> bool {
428        *self == ETF::FckIntN8
429    }
430    ///fSAMPLING=fDTS/2, N=6
431    #[inline(always)]
432    pub fn is_fdts_div2_n6(&self) -> bool {
433        *self == ETF::FdtsDiv2N6
434    }
435    ///fSAMPLING=fDTS/2, N=8
436    #[inline(always)]
437    pub fn is_fdts_div2_n8(&self) -> bool {
438        *self == ETF::FdtsDiv2N8
439    }
440    ///fSAMPLING=fDTS/4, N=6
441    #[inline(always)]
442    pub fn is_fdts_div4_n6(&self) -> bool {
443        *self == ETF::FdtsDiv4N6
444    }
445    ///fSAMPLING=fDTS/4, N=8
446    #[inline(always)]
447    pub fn is_fdts_div4_n8(&self) -> bool {
448        *self == ETF::FdtsDiv4N8
449    }
450    ///fSAMPLING=fDTS/8, N=6
451    #[inline(always)]
452    pub fn is_fdts_div8_n6(&self) -> bool {
453        *self == ETF::FdtsDiv8N6
454    }
455    ///fSAMPLING=fDTS/8, N=8
456    #[inline(always)]
457    pub fn is_fdts_div8_n8(&self) -> bool {
458        *self == ETF::FdtsDiv8N8
459    }
460    ///fSAMPLING=fDTS/16, N=5
461    #[inline(always)]
462    pub fn is_fdts_div16_n5(&self) -> bool {
463        *self == ETF::FdtsDiv16N5
464    }
465    ///fSAMPLING=fDTS/16, N=6
466    #[inline(always)]
467    pub fn is_fdts_div16_n6(&self) -> bool {
468        *self == ETF::FdtsDiv16N6
469    }
470    ///fSAMPLING=fDTS/16, N=8
471    #[inline(always)]
472    pub fn is_fdts_div16_n8(&self) -> bool {
473        *self == ETF::FdtsDiv16N8
474    }
475    ///fSAMPLING=fDTS/32, N=5
476    #[inline(always)]
477    pub fn is_fdts_div32_n5(&self) -> bool {
478        *self == ETF::FdtsDiv32N5
479    }
480    ///fSAMPLING=fDTS/32, N=6
481    #[inline(always)]
482    pub fn is_fdts_div32_n6(&self) -> bool {
483        *self == ETF::FdtsDiv32N6
484    }
485    ///fSAMPLING=fDTS/32, N=8
486    #[inline(always)]
487    pub fn is_fdts_div32_n8(&self) -> bool {
488        *self == ETF::FdtsDiv32N8
489    }
490}
491///Field `ETF` writer - External trigger filter
492pub type ETF_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ETF, crate::Safe>;
493impl<'a, REG> ETF_W<'a, REG>
494where
495    REG: crate::Writable + crate::RegisterSpec,
496    REG::Ux: From<u8>,
497{
498    ///No filter, sampling is done at fDTS
499    #[inline(always)]
500    pub fn no_filter(self) -> &'a mut crate::W<REG> {
501        self.variant(ETF::NoFilter)
502    }
503    ///fSAMPLING=fCK_INT, N=2
504    #[inline(always)]
505    pub fn fck_int_n2(self) -> &'a mut crate::W<REG> {
506        self.variant(ETF::FckIntN2)
507    }
508    ///fSAMPLING=fCK_INT, N=4
509    #[inline(always)]
510    pub fn fck_int_n4(self) -> &'a mut crate::W<REG> {
511        self.variant(ETF::FckIntN4)
512    }
513    ///fSAMPLING=fCK_INT, N=8
514    #[inline(always)]
515    pub fn fck_int_n8(self) -> &'a mut crate::W<REG> {
516        self.variant(ETF::FckIntN8)
517    }
518    ///fSAMPLING=fDTS/2, N=6
519    #[inline(always)]
520    pub fn fdts_div2_n6(self) -> &'a mut crate::W<REG> {
521        self.variant(ETF::FdtsDiv2N6)
522    }
523    ///fSAMPLING=fDTS/2, N=8
524    #[inline(always)]
525    pub fn fdts_div2_n8(self) -> &'a mut crate::W<REG> {
526        self.variant(ETF::FdtsDiv2N8)
527    }
528    ///fSAMPLING=fDTS/4, N=6
529    #[inline(always)]
530    pub fn fdts_div4_n6(self) -> &'a mut crate::W<REG> {
531        self.variant(ETF::FdtsDiv4N6)
532    }
533    ///fSAMPLING=fDTS/4, N=8
534    #[inline(always)]
535    pub fn fdts_div4_n8(self) -> &'a mut crate::W<REG> {
536        self.variant(ETF::FdtsDiv4N8)
537    }
538    ///fSAMPLING=fDTS/8, N=6
539    #[inline(always)]
540    pub fn fdts_div8_n6(self) -> &'a mut crate::W<REG> {
541        self.variant(ETF::FdtsDiv8N6)
542    }
543    ///fSAMPLING=fDTS/8, N=8
544    #[inline(always)]
545    pub fn fdts_div8_n8(self) -> &'a mut crate::W<REG> {
546        self.variant(ETF::FdtsDiv8N8)
547    }
548    ///fSAMPLING=fDTS/16, N=5
549    #[inline(always)]
550    pub fn fdts_div16_n5(self) -> &'a mut crate::W<REG> {
551        self.variant(ETF::FdtsDiv16N5)
552    }
553    ///fSAMPLING=fDTS/16, N=6
554    #[inline(always)]
555    pub fn fdts_div16_n6(self) -> &'a mut crate::W<REG> {
556        self.variant(ETF::FdtsDiv16N6)
557    }
558    ///fSAMPLING=fDTS/16, N=8
559    #[inline(always)]
560    pub fn fdts_div16_n8(self) -> &'a mut crate::W<REG> {
561        self.variant(ETF::FdtsDiv16N8)
562    }
563    ///fSAMPLING=fDTS/32, N=5
564    #[inline(always)]
565    pub fn fdts_div32_n5(self) -> &'a mut crate::W<REG> {
566        self.variant(ETF::FdtsDiv32N5)
567    }
568    ///fSAMPLING=fDTS/32, N=6
569    #[inline(always)]
570    pub fn fdts_div32_n6(self) -> &'a mut crate::W<REG> {
571        self.variant(ETF::FdtsDiv32N6)
572    }
573    ///fSAMPLING=fDTS/32, N=8
574    #[inline(always)]
575    pub fn fdts_div32_n8(self) -> &'a mut crate::W<REG> {
576        self.variant(ETF::FdtsDiv32N8)
577    }
578}
579/**External trigger prescaler
580
581Value on reset: 0*/
582#[cfg_attr(feature = "defmt", derive(defmt::Format))]
583#[derive(Clone, Copy, Debug, PartialEq, Eq)]
584#[repr(u8)]
585pub enum ETPS {
586    ///0: Prescaler OFF
587    Div1 = 0,
588    ///1: ETRP frequency divided by 2
589    Div2 = 1,
590    ///2: ETRP frequency divided by 4
591    Div4 = 2,
592    ///3: ETRP frequency divided by 8
593    Div8 = 3,
594}
595impl From<ETPS> for u8 {
596    #[inline(always)]
597    fn from(variant: ETPS) -> Self {
598        variant as _
599    }
600}
601impl crate::FieldSpec for ETPS {
602    type Ux = u8;
603}
604impl crate::IsEnum for ETPS {}
605///Field `ETPS` reader - External trigger prescaler
606pub type ETPS_R = crate::FieldReader<ETPS>;
607impl ETPS_R {
608    ///Get enumerated values variant
609    #[inline(always)]
610    pub const fn variant(&self) -> ETPS {
611        match self.bits {
612            0 => ETPS::Div1,
613            1 => ETPS::Div2,
614            2 => ETPS::Div4,
615            3 => ETPS::Div8,
616            _ => unreachable!(),
617        }
618    }
619    ///Prescaler OFF
620    #[inline(always)]
621    pub fn is_div1(&self) -> bool {
622        *self == ETPS::Div1
623    }
624    ///ETRP frequency divided by 2
625    #[inline(always)]
626    pub fn is_div2(&self) -> bool {
627        *self == ETPS::Div2
628    }
629    ///ETRP frequency divided by 4
630    #[inline(always)]
631    pub fn is_div4(&self) -> bool {
632        *self == ETPS::Div4
633    }
634    ///ETRP frequency divided by 8
635    #[inline(always)]
636    pub fn is_div8(&self) -> bool {
637        *self == ETPS::Div8
638    }
639}
640///Field `ETPS` writer - External trigger prescaler
641pub type ETPS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ETPS, crate::Safe>;
642impl<'a, REG> ETPS_W<'a, REG>
643where
644    REG: crate::Writable + crate::RegisterSpec,
645    REG::Ux: From<u8>,
646{
647    ///Prescaler OFF
648    #[inline(always)]
649    pub fn div1(self) -> &'a mut crate::W<REG> {
650        self.variant(ETPS::Div1)
651    }
652    ///ETRP frequency divided by 2
653    #[inline(always)]
654    pub fn div2(self) -> &'a mut crate::W<REG> {
655        self.variant(ETPS::Div2)
656    }
657    ///ETRP frequency divided by 4
658    #[inline(always)]
659    pub fn div4(self) -> &'a mut crate::W<REG> {
660        self.variant(ETPS::Div4)
661    }
662    ///ETRP frequency divided by 8
663    #[inline(always)]
664    pub fn div8(self) -> &'a mut crate::W<REG> {
665        self.variant(ETPS::Div8)
666    }
667}
668/**External clock enable
669
670Value on reset: 0*/
671#[cfg_attr(feature = "defmt", derive(defmt::Format))]
672#[derive(Clone, Copy, Debug, PartialEq, Eq)]
673pub enum ECE {
674    ///0: External clock mode 2 disabled
675    Disabled = 0,
676    ///1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
677    Enabled = 1,
678}
679impl From<ECE> for bool {
680    #[inline(always)]
681    fn from(variant: ECE) -> Self {
682        variant as u8 != 0
683    }
684}
685///Field `ECE` reader - External clock enable
686pub type ECE_R = crate::BitReader<ECE>;
687impl ECE_R {
688    ///Get enumerated values variant
689    #[inline(always)]
690    pub const fn variant(&self) -> ECE {
691        match self.bits {
692            false => ECE::Disabled,
693            true => ECE::Enabled,
694        }
695    }
696    ///External clock mode 2 disabled
697    #[inline(always)]
698    pub fn is_disabled(&self) -> bool {
699        *self == ECE::Disabled
700    }
701    ///External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
702    #[inline(always)]
703    pub fn is_enabled(&self) -> bool {
704        *self == ECE::Enabled
705    }
706}
707///Field `ECE` writer - External clock enable
708pub type ECE_W<'a, REG> = crate::BitWriter<'a, REG, ECE>;
709impl<'a, REG> ECE_W<'a, REG>
710where
711    REG: crate::Writable + crate::RegisterSpec,
712{
713    ///External clock mode 2 disabled
714    #[inline(always)]
715    pub fn disabled(self) -> &'a mut crate::W<REG> {
716        self.variant(ECE::Disabled)
717    }
718    ///External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
719    #[inline(always)]
720    pub fn enabled(self) -> &'a mut crate::W<REG> {
721        self.variant(ECE::Enabled)
722    }
723}
724/**External trigger polarity
725
726Value on reset: 0*/
727#[cfg_attr(feature = "defmt", derive(defmt::Format))]
728#[derive(Clone, Copy, Debug, PartialEq, Eq)]
729pub enum ETP {
730    ///0: ETR is noninverted, active at high level or rising edge
731    NotInverted = 0,
732    ///1: ETR is inverted, active at low level or falling edge
733    Inverted = 1,
734}
735impl From<ETP> for bool {
736    #[inline(always)]
737    fn from(variant: ETP) -> Self {
738        variant as u8 != 0
739    }
740}
741///Field `ETP` reader - External trigger polarity
742pub type ETP_R = crate::BitReader<ETP>;
743impl ETP_R {
744    ///Get enumerated values variant
745    #[inline(always)]
746    pub const fn variant(&self) -> ETP {
747        match self.bits {
748            false => ETP::NotInverted,
749            true => ETP::Inverted,
750        }
751    }
752    ///ETR is noninverted, active at high level or rising edge
753    #[inline(always)]
754    pub fn is_not_inverted(&self) -> bool {
755        *self == ETP::NotInverted
756    }
757    ///ETR is inverted, active at low level or falling edge
758    #[inline(always)]
759    pub fn is_inverted(&self) -> bool {
760        *self == ETP::Inverted
761    }
762}
763///Field `ETP` writer - External trigger polarity
764pub type ETP_W<'a, REG> = crate::BitWriter<'a, REG, ETP>;
765impl<'a, REG> ETP_W<'a, REG>
766where
767    REG: crate::Writable + crate::RegisterSpec,
768{
769    ///ETR is noninverted, active at high level or rising edge
770    #[inline(always)]
771    pub fn not_inverted(self) -> &'a mut crate::W<REG> {
772        self.variant(ETP::NotInverted)
773    }
774    ///ETR is inverted, active at low level or falling edge
775    #[inline(always)]
776    pub fn inverted(self) -> &'a mut crate::W<REG> {
777        self.variant(ETP::Inverted)
778    }
779}
780impl R {
781    ///Bits 0:2 - Slave mode selection
782    #[inline(always)]
783    pub fn sms(&self) -> SMS_R {
784        SMS_R::new((self.bits & 7) as u8)
785    }
786    ///Bit 3 - OCREF clear selection
787    #[inline(always)]
788    pub fn occs(&self) -> OCCS_R {
789        OCCS_R::new(((self.bits >> 3) & 1) != 0)
790    }
791    ///Bits 4:6 - Trigger selection
792    #[inline(always)]
793    pub fn ts(&self) -> TS_R {
794        TS_R::new(((self.bits >> 4) & 7) as u8)
795    }
796    ///Bit 7 - Master/Slave mode
797    #[inline(always)]
798    pub fn msm(&self) -> MSM_R {
799        MSM_R::new(((self.bits >> 7) & 1) != 0)
800    }
801    ///Bits 8:11 - External trigger filter
802    #[inline(always)]
803    pub fn etf(&self) -> ETF_R {
804        ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
805    }
806    ///Bits 12:13 - External trigger prescaler
807    #[inline(always)]
808    pub fn etps(&self) -> ETPS_R {
809        ETPS_R::new(((self.bits >> 12) & 3) as u8)
810    }
811    ///Bit 14 - External clock enable
812    #[inline(always)]
813    pub fn ece(&self) -> ECE_R {
814        ECE_R::new(((self.bits >> 14) & 1) != 0)
815    }
816    ///Bit 15 - External trigger polarity
817    #[inline(always)]
818    pub fn etp(&self) -> ETP_R {
819        ETP_R::new(((self.bits >> 15) & 1) != 0)
820    }
821}
822impl core::fmt::Debug for R {
823    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
824        f.debug_struct("SMCR")
825            .field("etp", &self.etp())
826            .field("ece", &self.ece())
827            .field("etps", &self.etps())
828            .field("etf", &self.etf())
829            .field("msm", &self.msm())
830            .field("ts", &self.ts())
831            .field("sms", &self.sms())
832            .field("occs", &self.occs())
833            .finish()
834    }
835}
836impl W {
837    ///Bits 0:2 - Slave mode selection
838    #[inline(always)]
839    pub fn sms(&mut self) -> SMS_W<SMCRrs> {
840        SMS_W::new(self, 0)
841    }
842    ///Bit 3 - OCREF clear selection
843    #[inline(always)]
844    pub fn occs(&mut self) -> OCCS_W<SMCRrs> {
845        OCCS_W::new(self, 3)
846    }
847    ///Bits 4:6 - Trigger selection
848    #[inline(always)]
849    pub fn ts(&mut self) -> TS_W<SMCRrs> {
850        TS_W::new(self, 4)
851    }
852    ///Bit 7 - Master/Slave mode
853    #[inline(always)]
854    pub fn msm(&mut self) -> MSM_W<SMCRrs> {
855        MSM_W::new(self, 7)
856    }
857    ///Bits 8:11 - External trigger filter
858    #[inline(always)]
859    pub fn etf(&mut self) -> ETF_W<SMCRrs> {
860        ETF_W::new(self, 8)
861    }
862    ///Bits 12:13 - External trigger prescaler
863    #[inline(always)]
864    pub fn etps(&mut self) -> ETPS_W<SMCRrs> {
865        ETPS_W::new(self, 12)
866    }
867    ///Bit 14 - External clock enable
868    #[inline(always)]
869    pub fn ece(&mut self) -> ECE_W<SMCRrs> {
870        ECE_W::new(self, 14)
871    }
872    ///Bit 15 - External trigger polarity
873    #[inline(always)]
874    pub fn etp(&mut self) -> ETP_W<SMCRrs> {
875        ETP_W::new(self, 15)
876    }
877}
878/**slave mode control register
879
880You can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
881
882See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM2:SMCR)*/
883pub struct SMCRrs;
884impl crate::RegisterSpec for SMCRrs {
885    type Ux = u32;
886}
887///`read()` method returns [`smcr::R`](R) reader structure
888impl crate::Readable for SMCRrs {}
889///`write(|w| ..)` method takes [`smcr::W`](W) writer structure
890impl crate::Writable for SMCRrs {
891    type Safety = crate::Unsafe;
892}
893///`reset()` method sets SMCR to value 0
894impl crate::Resettable for SMCRrs {}
stm32f1/stm32f100/tim2/smcr.rs

stm32f1/stm32f100/tim2/
smcr.rs
