stm32f1/stm32f100/tim12/smcr.rs
1///Register `SMCR` reader
2pub type R = crate::R<SMCRrs>;
3///Register `SMCR` writer
4pub type W = crate::W<SMCRrs>;
5/**Slave mode selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum SMS {
12 ///0: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
13 Disabled = 0,
14 ///4: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
15 ResetMode = 4,
16 ///5: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
17 GatedMode = 5,
18 ///6: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
19 TriggerMode = 6,
20 ///7: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
21 ExtClockMode = 7,
22}
23impl From<SMS> for u8 {
24 #[inline(always)]
25 fn from(variant: SMS) -> Self {
26 variant as _
27 }
28}
29impl crate::FieldSpec for SMS {
30 type Ux = u8;
31}
32impl crate::IsEnum for SMS {}
33///Field `SMS` reader - Slave mode selection
34pub type SMS_R = crate::FieldReader<SMS>;
35impl SMS_R {
36 ///Get enumerated values variant
37 #[inline(always)]
38 pub const fn variant(&self) -> Option<SMS> {
39 match self.bits {
40 0 => Some(SMS::Disabled),
41 4 => Some(SMS::ResetMode),
42 5 => Some(SMS::GatedMode),
43 6 => Some(SMS::TriggerMode),
44 7 => Some(SMS::ExtClockMode),
45 _ => None,
46 }
47 }
48 ///Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
49 #[inline(always)]
50 pub fn is_disabled(&self) -> bool {
51 *self == SMS::Disabled
52 }
53 ///Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
54 #[inline(always)]
55 pub fn is_reset_mode(&self) -> bool {
56 *self == SMS::ResetMode
57 }
58 ///Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
59 #[inline(always)]
60 pub fn is_gated_mode(&self) -> bool {
61 *self == SMS::GatedMode
62 }
63 ///Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
64 #[inline(always)]
65 pub fn is_trigger_mode(&self) -> bool {
66 *self == SMS::TriggerMode
67 }
68 ///External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
69 #[inline(always)]
70 pub fn is_ext_clock_mode(&self) -> bool {
71 *self == SMS::ExtClockMode
72 }
73}
74///Field `SMS` writer - Slave mode selection
75pub type SMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SMS>;
76impl<'a, REG> SMS_W<'a, REG>
77where
78 REG: crate::Writable + crate::RegisterSpec,
79 REG::Ux: From<u8>,
80{
81 ///Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
82 #[inline(always)]
83 pub fn disabled(self) -> &'a mut crate::W<REG> {
84 self.variant(SMS::Disabled)
85 }
86 ///Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
87 #[inline(always)]
88 pub fn reset_mode(self) -> &'a mut crate::W<REG> {
89 self.variant(SMS::ResetMode)
90 }
91 ///Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
92 #[inline(always)]
93 pub fn gated_mode(self) -> &'a mut crate::W<REG> {
94 self.variant(SMS::GatedMode)
95 }
96 ///Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
97 #[inline(always)]
98 pub fn trigger_mode(self) -> &'a mut crate::W<REG> {
99 self.variant(SMS::TriggerMode)
100 }
101 ///External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
102 #[inline(always)]
103 pub fn ext_clock_mode(self) -> &'a mut crate::W<REG> {
104 self.variant(SMS::ExtClockMode)
105 }
106}
107///Field `TS` reader - Trigger selection
108pub type TS_R = crate::FieldReader;
109///Field `TS` writer - Trigger selection
110pub type TS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
111/**Master/Slave mode
112
113Value on reset: 0*/
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum MSM {
117 ///0: No action
118 NoSync = 0,
119 ///1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
120 Sync = 1,
121}
122impl From<MSM> for bool {
123 #[inline(always)]
124 fn from(variant: MSM) -> Self {
125 variant as u8 != 0
126 }
127}
128///Field `MSM` reader - Master/Slave mode
129pub type MSM_R = crate::BitReader<MSM>;
130impl MSM_R {
131 ///Get enumerated values variant
132 #[inline(always)]
133 pub const fn variant(&self) -> MSM {
134 match self.bits {
135 false => MSM::NoSync,
136 true => MSM::Sync,
137 }
138 }
139 ///No action
140 #[inline(always)]
141 pub fn is_no_sync(&self) -> bool {
142 *self == MSM::NoSync
143 }
144 ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
145 #[inline(always)]
146 pub fn is_sync(&self) -> bool {
147 *self == MSM::Sync
148 }
149}
150///Field `MSM` writer - Master/Slave mode
151pub type MSM_W<'a, REG> = crate::BitWriter<'a, REG, MSM>;
152impl<'a, REG> MSM_W<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 ///No action
157 #[inline(always)]
158 pub fn no_sync(self) -> &'a mut crate::W<REG> {
159 self.variant(MSM::NoSync)
160 }
161 ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
162 #[inline(always)]
163 pub fn sync(self) -> &'a mut crate::W<REG> {
164 self.variant(MSM::Sync)
165 }
166}
167impl R {
168 ///Bits 0:2 - Slave mode selection
169 #[inline(always)]
170 pub fn sms(&self) -> SMS_R {
171 SMS_R::new((self.bits & 7) as u8)
172 }
173 ///Bits 4:6 - Trigger selection
174 #[inline(always)]
175 pub fn ts(&self) -> TS_R {
176 TS_R::new(((self.bits >> 4) & 7) as u8)
177 }
178 ///Bit 7 - Master/Slave mode
179 #[inline(always)]
180 pub fn msm(&self) -> MSM_R {
181 MSM_R::new(((self.bits >> 7) & 1) != 0)
182 }
183}
184impl core::fmt::Debug for R {
185 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
186 f.debug_struct("SMCR")
187 .field("msm", &self.msm())
188 .field("ts", &self.ts())
189 .field("sms", &self.sms())
190 .finish()
191 }
192}
193impl W {
194 ///Bits 0:2 - Slave mode selection
195 #[inline(always)]
196 pub fn sms(&mut self) -> SMS_W<SMCRrs> {
197 SMS_W::new(self, 0)
198 }
199 ///Bits 4:6 - Trigger selection
200 #[inline(always)]
201 pub fn ts(&mut self) -> TS_W<SMCRrs> {
202 TS_W::new(self, 4)
203 }
204 ///Bit 7 - Master/Slave mode
205 #[inline(always)]
206 pub fn msm(&mut self) -> MSM_W<SMCRrs> {
207 MSM_W::new(self, 7)
208 }
209}
210/**slave mode control register
211
212You can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12:SMCR)*/
215pub struct SMCRrs;
216impl crate::RegisterSpec for SMCRrs {
217 type Ux = u32;
218}
219///`read()` method returns [`smcr::R`](R) reader structure
220impl crate::Readable for SMCRrs {}
221///`write(|w| ..)` method takes [`smcr::W`](W) writer structure
222impl crate::Writable for SMCRrs {
223 type Safety = crate::Unsafe;
224}
225///`reset()` method sets SMCR to value 0
226impl crate::Resettable for SMCRrs {}