stm32f1/stm32f100/rtc/
crh.rs

1///Register `CRH` reader
2pub type R = crate::R<CRHrs>;
3///Register `CRH` writer
4pub type W = crate::W<CRHrs>;
5/**Second interrupt Enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum SECIE {
11    ///0: Second interrupt is masked
12    Disabled = 0,
13    ///1: Second interrupt is enabled
14    Enabled = 1,
15}
16impl From<SECIE> for bool {
17    #[inline(always)]
18    fn from(variant: SECIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `SECIE` reader - Second interrupt Enable
23pub type SECIE_R = crate::BitReader<SECIE>;
24impl SECIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> SECIE {
28        match self.bits {
29            false => SECIE::Disabled,
30            true => SECIE::Enabled,
31        }
32    }
33    ///Second interrupt is masked
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == SECIE::Disabled
37    }
38    ///Second interrupt is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == SECIE::Enabled
42    }
43}
44///Field `SECIE` writer - Second interrupt Enable
45pub type SECIE_W<'a, REG> = crate::BitWriter<'a, REG, SECIE>;
46impl<'a, REG> SECIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Second interrupt is masked
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(SECIE::Disabled)
54    }
55    ///Second interrupt is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(SECIE::Enabled)
59    }
60}
61/**Alarm interrupt Enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum ALRIE {
67    ///0: Alarm interrupt is masked
68    Disabled = 0,
69    ///1: Alarm interrupt is enabled
70    Enabled = 1,
71}
72impl From<ALRIE> for bool {
73    #[inline(always)]
74    fn from(variant: ALRIE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `ALRIE` reader - Alarm interrupt Enable
79pub type ALRIE_R = crate::BitReader<ALRIE>;
80impl ALRIE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> ALRIE {
84        match self.bits {
85            false => ALRIE::Disabled,
86            true => ALRIE::Enabled,
87        }
88    }
89    ///Alarm interrupt is masked
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == ALRIE::Disabled
93    }
94    ///Alarm interrupt is enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == ALRIE::Enabled
98    }
99}
100///Field `ALRIE` writer - Alarm interrupt Enable
101pub type ALRIE_W<'a, REG> = crate::BitWriter<'a, REG, ALRIE>;
102impl<'a, REG> ALRIE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Alarm interrupt is masked
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(ALRIE::Disabled)
110    }
111    ///Alarm interrupt is enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(ALRIE::Enabled)
115    }
116}
117/**Overflow interrupt Enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum OWIE {
123    ///0: Overflow interrupt is masked
124    Disabled = 0,
125    ///1: Overflow interrupt is enabled
126    Enabled = 1,
127}
128impl From<OWIE> for bool {
129    #[inline(always)]
130    fn from(variant: OWIE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `OWIE` reader - Overflow interrupt Enable
135pub type OWIE_R = crate::BitReader<OWIE>;
136impl OWIE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> OWIE {
140        match self.bits {
141            false => OWIE::Disabled,
142            true => OWIE::Enabled,
143        }
144    }
145    ///Overflow interrupt is masked
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == OWIE::Disabled
149    }
150    ///Overflow interrupt is enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == OWIE::Enabled
154    }
155}
156///Field `OWIE` writer - Overflow interrupt Enable
157pub type OWIE_W<'a, REG> = crate::BitWriter<'a, REG, OWIE>;
158impl<'a, REG> OWIE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Overflow interrupt is masked
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(OWIE::Disabled)
166    }
167    ///Overflow interrupt is enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(OWIE::Enabled)
171    }
172}
173impl R {
174    ///Bit 0 - Second interrupt Enable
175    #[inline(always)]
176    pub fn secie(&self) -> SECIE_R {
177        SECIE_R::new((self.bits & 1) != 0)
178    }
179    ///Bit 1 - Alarm interrupt Enable
180    #[inline(always)]
181    pub fn alrie(&self) -> ALRIE_R {
182        ALRIE_R::new(((self.bits >> 1) & 1) != 0)
183    }
184    ///Bit 2 - Overflow interrupt Enable
185    #[inline(always)]
186    pub fn owie(&self) -> OWIE_R {
187        OWIE_R::new(((self.bits >> 2) & 1) != 0)
188    }
189}
190impl core::fmt::Debug for R {
191    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
192        f.debug_struct("CRH")
193            .field("secie", &self.secie())
194            .field("alrie", &self.alrie())
195            .field("owie", &self.owie())
196            .finish()
197    }
198}
199impl W {
200    ///Bit 0 - Second interrupt Enable
201    #[inline(always)]
202    pub fn secie(&mut self) -> SECIE_W<CRHrs> {
203        SECIE_W::new(self, 0)
204    }
205    ///Bit 1 - Alarm interrupt Enable
206    #[inline(always)]
207    pub fn alrie(&mut self) -> ALRIE_W<CRHrs> {
208        ALRIE_W::new(self, 1)
209    }
210    ///Bit 2 - Overflow interrupt Enable
211    #[inline(always)]
212    pub fn owie(&mut self) -> OWIE_W<CRHrs> {
213        OWIE_W::new(self, 2)
214    }
215}
216/**RTC Control Register High
217
218You can [`read`](crate::Reg::read) this register and get [`crh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
219
220See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#RTC:CRH)*/
221pub struct CRHrs;
222impl crate::RegisterSpec for CRHrs {
223    type Ux = u32;
224}
225///`read()` method returns [`crh::R`](R) reader structure
226impl crate::Readable for CRHrs {}
227///`write(|w| ..)` method takes [`crh::W`](W) writer structure
228impl crate::Writable for CRHrs {
229    type Safety = crate::Unsafe;
230}
231///`reset()` method sets CRH to value 0
232impl crate::Resettable for CRHrs {}
stm32f1/stm32f100/rtc/crh.rs

stm32f1/stm32f100/rtc/
crh.rs
