stm32f1/stm32f100/gpioa/
lckr.rs

1///Register `LCKR` reader
2pub type R = crate::R<LCKRrs>;
3///Register `LCKR` writer
4pub type W = crate::W<LCKRrs>;
5/**Port A Lock bit %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum LOCK {
11    ///0: Port configuration not locked
12    Unlocked = 0,
13    ///1: Port configuration locked
14    Locked = 1,
15}
16impl From<LOCK> for bool {
17    #[inline(always)]
18    fn from(variant: LOCK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `LCK(0-15)` reader - Port A Lock bit %s
23pub type LCK_R = crate::BitReader<LOCK>;
24impl LCK_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> LOCK {
28        match self.bits {
29            false => LOCK::Unlocked,
30            true => LOCK::Locked,
31        }
32    }
33    ///Port configuration not locked
34    #[inline(always)]
35    pub fn is_unlocked(&self) -> bool {
36        *self == LOCK::Unlocked
37    }
38    ///Port configuration locked
39    #[inline(always)]
40    pub fn is_locked(&self) -> bool {
41        *self == LOCK::Locked
42    }
43}
44///Field `LCK(0-15)` writer - Port A Lock bit %s
45pub type LCK_W<'a, REG> = crate::BitWriter<'a, REG, LOCK>;
46impl<'a, REG> LCK_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Port configuration not locked
51    #[inline(always)]
52    pub fn unlocked(self) -> &'a mut crate::W<REG> {
53        self.variant(LOCK::Unlocked)
54    }
55    ///Port configuration locked
56    #[inline(always)]
57    pub fn locked(self) -> &'a mut crate::W<REG> {
58        self.variant(LOCK::Locked)
59    }
60}
61/**Lock key
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum LOCK_KEY {
67    ///0: Port configuration lock key not active
68    NotActive = 0,
69    ///1: Port configuration lock key active
70    Active = 1,
71}
72impl From<LOCK_KEY> for bool {
73    #[inline(always)]
74    fn from(variant: LOCK_KEY) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `LCKK` reader - Lock key
79pub type LCKK_R = crate::BitReader<LOCK_KEY>;
80impl LCKK_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> LOCK_KEY {
84        match self.bits {
85            false => LOCK_KEY::NotActive,
86            true => LOCK_KEY::Active,
87        }
88    }
89    ///Port configuration lock key not active
90    #[inline(always)]
91    pub fn is_not_active(&self) -> bool {
92        *self == LOCK_KEY::NotActive
93    }
94    ///Port configuration lock key active
95    #[inline(always)]
96    pub fn is_active(&self) -> bool {
97        *self == LOCK_KEY::Active
98    }
99}
100///Field `LCKK` writer - Lock key
101pub type LCKK_W<'a, REG> = crate::BitWriter<'a, REG, LOCK_KEY>;
102impl<'a, REG> LCKK_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Port configuration lock key not active
107    #[inline(always)]
108    pub fn not_active(self) -> &'a mut crate::W<REG> {
109        self.variant(LOCK_KEY::NotActive)
110    }
111    ///Port configuration lock key active
112    #[inline(always)]
113    pub fn active(self) -> &'a mut crate::W<REG> {
114        self.variant(LOCK_KEY::Active)
115    }
116}
117impl R {
118    ///Port A Lock bit (0-15)
119    ///
120    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `LCK0` field.</div>
121    #[inline(always)]
122    pub fn lck(&self, n: u8) -> LCK_R {
123        #[allow(clippy::no_effect)]
124        [(); 16][n as usize];
125        LCK_R::new(((self.bits >> n) & 1) != 0)
126    }
127    ///Iterator for array of:
128    ///Port A Lock bit (0-15)
129    #[inline(always)]
130    pub fn lck_iter(&self) -> impl Iterator<Item = LCK_R> + '_ {
131        (0..16).map(move |n| LCK_R::new(((self.bits >> n) & 1) != 0))
132    }
133    ///Bit 0 - Port A Lock bit 0
134    #[inline(always)]
135    pub fn lck0(&self) -> LCK_R {
136        LCK_R::new((self.bits & 1) != 0)
137    }
138    ///Bit 1 - Port A Lock bit 1
139    #[inline(always)]
140    pub fn lck1(&self) -> LCK_R {
141        LCK_R::new(((self.bits >> 1) & 1) != 0)
142    }
143    ///Bit 2 - Port A Lock bit 2
144    #[inline(always)]
145    pub fn lck2(&self) -> LCK_R {
146        LCK_R::new(((self.bits >> 2) & 1) != 0)
147    }
148    ///Bit 3 - Port A Lock bit 3
149    #[inline(always)]
150    pub fn lck3(&self) -> LCK_R {
151        LCK_R::new(((self.bits >> 3) & 1) != 0)
152    }
153    ///Bit 4 - Port A Lock bit 4
154    #[inline(always)]
155    pub fn lck4(&self) -> LCK_R {
156        LCK_R::new(((self.bits >> 4) & 1) != 0)
157    }
158    ///Bit 5 - Port A Lock bit 5
159    #[inline(always)]
160    pub fn lck5(&self) -> LCK_R {
161        LCK_R::new(((self.bits >> 5) & 1) != 0)
162    }
163    ///Bit 6 - Port A Lock bit 6
164    #[inline(always)]
165    pub fn lck6(&self) -> LCK_R {
166        LCK_R::new(((self.bits >> 6) & 1) != 0)
167    }
168    ///Bit 7 - Port A Lock bit 7
169    #[inline(always)]
170    pub fn lck7(&self) -> LCK_R {
171        LCK_R::new(((self.bits >> 7) & 1) != 0)
172    }
173    ///Bit 8 - Port A Lock bit 8
174    #[inline(always)]
175    pub fn lck8(&self) -> LCK_R {
176        LCK_R::new(((self.bits >> 8) & 1) != 0)
177    }
178    ///Bit 9 - Port A Lock bit 9
179    #[inline(always)]
180    pub fn lck9(&self) -> LCK_R {
181        LCK_R::new(((self.bits >> 9) & 1) != 0)
182    }
183    ///Bit 10 - Port A Lock bit 10
184    #[inline(always)]
185    pub fn lck10(&self) -> LCK_R {
186        LCK_R::new(((self.bits >> 10) & 1) != 0)
187    }
188    ///Bit 11 - Port A Lock bit 11
189    #[inline(always)]
190    pub fn lck11(&self) -> LCK_R {
191        LCK_R::new(((self.bits >> 11) & 1) != 0)
192    }
193    ///Bit 12 - Port A Lock bit 12
194    #[inline(always)]
195    pub fn lck12(&self) -> LCK_R {
196        LCK_R::new(((self.bits >> 12) & 1) != 0)
197    }
198    ///Bit 13 - Port A Lock bit 13
199    #[inline(always)]
200    pub fn lck13(&self) -> LCK_R {
201        LCK_R::new(((self.bits >> 13) & 1) != 0)
202    }
203    ///Bit 14 - Port A Lock bit 14
204    #[inline(always)]
205    pub fn lck14(&self) -> LCK_R {
206        LCK_R::new(((self.bits >> 14) & 1) != 0)
207    }
208    ///Bit 15 - Port A Lock bit 15
209    #[inline(always)]
210    pub fn lck15(&self) -> LCK_R {
211        LCK_R::new(((self.bits >> 15) & 1) != 0)
212    }
213    ///Bit 16 - Lock key
214    #[inline(always)]
215    pub fn lckk(&self) -> LCKK_R {
216        LCKK_R::new(((self.bits >> 16) & 1) != 0)
217    }
218}
219impl core::fmt::Debug for R {
220    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
221        f.debug_struct("LCKR")
222            .field("lck0", &self.lck0())
223            .field("lck1", &self.lck1())
224            .field("lck2", &self.lck2())
225            .field("lck3", &self.lck3())
226            .field("lck4", &self.lck4())
227            .field("lck5", &self.lck5())
228            .field("lck6", &self.lck6())
229            .field("lck7", &self.lck7())
230            .field("lck8", &self.lck8())
231            .field("lck9", &self.lck9())
232            .field("lck10", &self.lck10())
233            .field("lck11", &self.lck11())
234            .field("lck12", &self.lck12())
235            .field("lck13", &self.lck13())
236            .field("lck14", &self.lck14())
237            .field("lck15", &self.lck15())
238            .field("lckk", &self.lckk())
239            .finish()
240    }
241}
242impl W {
243    ///Port A Lock bit (0-15)
244    ///
245    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `LCK0` field.</div>
246    #[inline(always)]
247    pub fn lck(&mut self, n: u8) -> LCK_W<LCKRrs> {
248        #[allow(clippy::no_effect)]
249        [(); 16][n as usize];
250        LCK_W::new(self, n)
251    }
252    ///Bit 0 - Port A Lock bit 0
253    #[inline(always)]
254    pub fn lck0(&mut self) -> LCK_W<LCKRrs> {
255        LCK_W::new(self, 0)
256    }
257    ///Bit 1 - Port A Lock bit 1
258    #[inline(always)]
259    pub fn lck1(&mut self) -> LCK_W<LCKRrs> {
260        LCK_W::new(self, 1)
261    }
262    ///Bit 2 - Port A Lock bit 2
263    #[inline(always)]
264    pub fn lck2(&mut self) -> LCK_W<LCKRrs> {
265        LCK_W::new(self, 2)
266    }
267    ///Bit 3 - Port A Lock bit 3
268    #[inline(always)]
269    pub fn lck3(&mut self) -> LCK_W<LCKRrs> {
270        LCK_W::new(self, 3)
271    }
272    ///Bit 4 - Port A Lock bit 4
273    #[inline(always)]
274    pub fn lck4(&mut self) -> LCK_W<LCKRrs> {
275        LCK_W::new(self, 4)
276    }
277    ///Bit 5 - Port A Lock bit 5
278    #[inline(always)]
279    pub fn lck5(&mut self) -> LCK_W<LCKRrs> {
280        LCK_W::new(self, 5)
281    }
282    ///Bit 6 - Port A Lock bit 6
283    #[inline(always)]
284    pub fn lck6(&mut self) -> LCK_W<LCKRrs> {
285        LCK_W::new(self, 6)
286    }
287    ///Bit 7 - Port A Lock bit 7
288    #[inline(always)]
289    pub fn lck7(&mut self) -> LCK_W<LCKRrs> {
290        LCK_W::new(self, 7)
291    }
292    ///Bit 8 - Port A Lock bit 8
293    #[inline(always)]
294    pub fn lck8(&mut self) -> LCK_W<LCKRrs> {
295        LCK_W::new(self, 8)
296    }
297    ///Bit 9 - Port A Lock bit 9
298    #[inline(always)]
299    pub fn lck9(&mut self) -> LCK_W<LCKRrs> {
300        LCK_W::new(self, 9)
301    }
302    ///Bit 10 - Port A Lock bit 10
303    #[inline(always)]
304    pub fn lck10(&mut self) -> LCK_W<LCKRrs> {
305        LCK_W::new(self, 10)
306    }
307    ///Bit 11 - Port A Lock bit 11
308    #[inline(always)]
309    pub fn lck11(&mut self) -> LCK_W<LCKRrs> {
310        LCK_W::new(self, 11)
311    }
312    ///Bit 12 - Port A Lock bit 12
313    #[inline(always)]
314    pub fn lck12(&mut self) -> LCK_W<LCKRrs> {
315        LCK_W::new(self, 12)
316    }
317    ///Bit 13 - Port A Lock bit 13
318    #[inline(always)]
319    pub fn lck13(&mut self) -> LCK_W<LCKRrs> {
320        LCK_W::new(self, 13)
321    }
322    ///Bit 14 - Port A Lock bit 14
323    #[inline(always)]
324    pub fn lck14(&mut self) -> LCK_W<LCKRrs> {
325        LCK_W::new(self, 14)
326    }
327    ///Bit 15 - Port A Lock bit 15
328    #[inline(always)]
329    pub fn lck15(&mut self) -> LCK_W<LCKRrs> {
330        LCK_W::new(self, 15)
331    }
332    ///Bit 16 - Lock key
333    #[inline(always)]
334    pub fn lckk(&mut self) -> LCKK_W<LCKRrs> {
335        LCKK_W::new(self, 16)
336    }
337}
338/**Port configuration lock register
339
340You can [`read`](crate::Reg::read) this register and get [`lckr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lckr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
341
342See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA:LCKR)*/
343pub struct LCKRrs;
344impl crate::RegisterSpec for LCKRrs {
345    type Ux = u32;
346}
347///`read()` method returns [`lckr::R`](R) reader structure
348impl crate::Readable for LCKRrs {}
349///`write(|w| ..)` method takes [`lckr::W`](W) writer structure
350impl crate::Writable for LCKRrs {
351    type Safety = crate::Unsafe;
352}
353///`reset()` method sets LCKR to value 0
354impl crate::Resettable for LCKRrs {}
stm32f1/stm32f100/gpioa/lckr.rs

stm32f1/stm32f100/gpioa/
lckr.rs
