stm32f1/stm32f107/tim8/
egr.rs

1#[doc = "Register `EGR` writer"]
2pub struct W(crate::W<EGR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<EGR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<EGR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<EGR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `BG` writer - Break generation"]
23pub type BG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
24#[doc = "Trigger generation\n\nValue on reset: 0"]
25#[derive(Clone, Copy, Debug, PartialEq)]
26pub enum TG_AW {
27    #[doc = "1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."]
28    Trigger = 1,
29}
30impl From<TG_AW> for bool {
31    #[inline(always)]
32    fn from(variant: TG_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `TG` writer - Trigger generation"]
37pub type TG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, TG_AW, O>;
38impl<'a, const O: u8> TG_W<'a, O> {
39    #[doc = "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."]
40    #[inline(always)]
41    pub fn trigger(self) -> &'a mut W {
42        self.variant(TG_AW::Trigger)
43    }
44}
45#[doc = "Field `COMG` writer - Capture/Compare control update generation"]
46pub type COMG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
47#[doc = "Capture/compare 4 generation"]
48pub use CC1G_AW as CC4G_AW;
49#[doc = "Capture/compare 3 generation"]
50pub use CC1G_AW as CC3G_AW;
51#[doc = "Capture/compare 2 generation"]
52pub use CC1G_AW as CC2G_AW;
53#[doc = "Field `CC4G` writer - Capture/compare 4 generation"]
54pub use CC1G_W as CC4G_W;
55#[doc = "Field `CC3G` writer - Capture/compare 3 generation"]
56pub use CC1G_W as CC3G_W;
57#[doc = "Field `CC2G` writer - Capture/compare 2 generation"]
58pub use CC1G_W as CC2G_W;
59#[doc = "Capture/compare 1 generation\n\nValue on reset: 0"]
60#[derive(Clone, Copy, Debug, PartialEq)]
61pub enum CC1G_AW {
62    #[doc = "1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."]
63    Trigger = 1,
64}
65impl From<CC1G_AW> for bool {
66    #[inline(always)]
67    fn from(variant: CC1G_AW) -> Self {
68        variant as u8 != 0
69    }
70}
71#[doc = "Field `CC1G` writer - Capture/compare 1 generation"]
72pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, CC1G_AW, O>;
73impl<'a, const O: u8> CC1G_W<'a, O> {
74    #[doc = "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."]
75    #[inline(always)]
76    pub fn trigger(self) -> &'a mut W {
77        self.variant(CC1G_AW::Trigger)
78    }
79}
80#[doc = "Update generation\n\nValue on reset: 0"]
81#[derive(Clone, Copy, Debug, PartialEq)]
82pub enum UG_AW {
83    #[doc = "1: Re-initializes the timer counter and generates an update of the registers."]
84    Update = 1,
85}
86impl From<UG_AW> for bool {
87    #[inline(always)]
88    fn from(variant: UG_AW) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `UG` writer - Update generation"]
93pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, UG_AW, O>;
94impl<'a, const O: u8> UG_W<'a, O> {
95    #[doc = "Re-initializes the timer counter and generates an update of the registers."]
96    #[inline(always)]
97    pub fn update(self) -> &'a mut W {
98        self.variant(UG_AW::Update)
99    }
100}
101impl W {
102    #[doc = "Bit 7 - Break generation"]
103    #[inline(always)]
104    pub fn bg(&mut self) -> BG_W<7> {
105        BG_W::new(self)
106    }
107    #[doc = "Bit 6 - Trigger generation"]
108    #[inline(always)]
109    pub fn tg(&mut self) -> TG_W<6> {
110        TG_W::new(self)
111    }
112    #[doc = "Bit 5 - Capture/Compare control update generation"]
113    #[inline(always)]
114    pub fn comg(&mut self) -> COMG_W<5> {
115        COMG_W::new(self)
116    }
117    #[doc = "Bit 4 - Capture/compare 4 generation"]
118    #[inline(always)]
119    pub fn cc4g(&mut self) -> CC4G_W<4> {
120        CC4G_W::new(self)
121    }
122    #[doc = "Bit 3 - Capture/compare 3 generation"]
123    #[inline(always)]
124    pub fn cc3g(&mut self) -> CC3G_W<3> {
125        CC3G_W::new(self)
126    }
127    #[doc = "Bit 2 - Capture/compare 2 generation"]
128    #[inline(always)]
129    pub fn cc2g(&mut self) -> CC2G_W<2> {
130        CC2G_W::new(self)
131    }
132    #[doc = "Bit 1 - Capture/compare 1 generation"]
133    #[inline(always)]
134    pub fn cc1g(&mut self) -> CC1G_W<1> {
135        CC1G_W::new(self)
136    }
137    #[doc = "Bit 0 - Update generation"]
138    #[inline(always)]
139    pub fn ug(&mut self) -> UG_W<0> {
140        UG_W::new(self)
141    }
142    #[doc = "Writes raw bits to the register."]
143    #[inline(always)]
144    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
145        self.0.bits(bits);
146        self
147    }
148}
149#[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"]
150pub struct EGR_SPEC;
151impl crate::RegisterSpec for EGR_SPEC {
152    type Ux = u32;
153}
154#[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"]
155impl crate::Writable for EGR_SPEC {
156    type Writer = W;
157}
158#[doc = "`reset()` method sets EGR to value 0"]
159impl crate::Resettable for EGR_SPEC {
160    #[inline(always)]
161    fn reset_value() -> Self::Ux {
162        0
163    }
164}
stm32f1/stm32f107/tim8/egr.rs

stm32f1/stm32f107/tim8/
egr.rs
