stm32f1/stm32f107/tim13/
ccmr1_output.rs

1#[doc = "Register `CCMR1_Output` reader"]
2pub struct R(crate::R<CCMR1_OUTPUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCMR1_OUTPUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCMR1_OUTPUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCMR1_OUTPUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CCMR1_Output` writer"]
17pub struct W(crate::W<CCMR1_OUTPUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCMR1_OUTPUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCMR1_OUTPUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCMR1_OUTPUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
38pub type CC1S_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
40pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
41#[doc = "Field `OC1FE` reader - Output compare 1 fast enable"]
42pub type OC1FE_R = crate::BitReader<bool>;
43#[doc = "Field `OC1FE` writer - Output compare 1 fast enable"]
44pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
45#[doc = "Field `OC1PE` reader - Output Compare 1 preload enable"]
46pub type OC1PE_R = crate::BitReader<bool>;
47#[doc = "Field `OC1PE` writer - Output Compare 1 preload enable"]
48pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
49#[doc = "Output Compare 1 mode\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq)]
51#[repr(u8)]
52pub enum OC1M_A {
53    #[doc = "0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
54    Frozen = 0,
55    #[doc = "1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
56    ActiveOnMatch = 1,
57    #[doc = "2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
58    InactiveOnMatch = 2,
59    #[doc = "3: OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
60    Toggle = 3,
61    #[doc = "4: OCyREF is forced low"]
62    ForceInactive = 4,
63    #[doc = "5: OCyREF is forced high"]
64    ForceActive = 5,
65    #[doc = "6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
66    PwmMode1 = 6,
67    #[doc = "7: Inversely to PwmMode1"]
68    PwmMode2 = 7,
69}
70impl From<OC1M_A> for u8 {
71    #[inline(always)]
72    fn from(variant: OC1M_A) -> Self {
73        variant as _
74    }
75}
76#[doc = "Field `OC1M` reader - Output Compare 1 mode"]
77pub type OC1M_R = crate::FieldReader<u8, OC1M_A>;
78impl OC1M_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> OC1M_A {
82        match self.bits {
83            0 => OC1M_A::Frozen,
84            1 => OC1M_A::ActiveOnMatch,
85            2 => OC1M_A::InactiveOnMatch,
86            3 => OC1M_A::Toggle,
87            4 => OC1M_A::ForceInactive,
88            5 => OC1M_A::ForceActive,
89            6 => OC1M_A::PwmMode1,
90            7 => OC1M_A::PwmMode2,
91            _ => unreachable!(),
92        }
93    }
94    #[doc = "Checks if the value of the field is `Frozen`"]
95    #[inline(always)]
96    pub fn is_frozen(&self) -> bool {
97        *self == OC1M_A::Frozen
98    }
99    #[doc = "Checks if the value of the field is `ActiveOnMatch`"]
100    #[inline(always)]
101    pub fn is_active_on_match(&self) -> bool {
102        *self == OC1M_A::ActiveOnMatch
103    }
104    #[doc = "Checks if the value of the field is `InactiveOnMatch`"]
105    #[inline(always)]
106    pub fn is_inactive_on_match(&self) -> bool {
107        *self == OC1M_A::InactiveOnMatch
108    }
109    #[doc = "Checks if the value of the field is `Toggle`"]
110    #[inline(always)]
111    pub fn is_toggle(&self) -> bool {
112        *self == OC1M_A::Toggle
113    }
114    #[doc = "Checks if the value of the field is `ForceInactive`"]
115    #[inline(always)]
116    pub fn is_force_inactive(&self) -> bool {
117        *self == OC1M_A::ForceInactive
118    }
119    #[doc = "Checks if the value of the field is `ForceActive`"]
120    #[inline(always)]
121    pub fn is_force_active(&self) -> bool {
122        *self == OC1M_A::ForceActive
123    }
124    #[doc = "Checks if the value of the field is `PwmMode1`"]
125    #[inline(always)]
126    pub fn is_pwm_mode1(&self) -> bool {
127        *self == OC1M_A::PwmMode1
128    }
129    #[doc = "Checks if the value of the field is `PwmMode2`"]
130    #[inline(always)]
131    pub fn is_pwm_mode2(&self) -> bool {
132        *self == OC1M_A::PwmMode2
133    }
134}
135#[doc = "Field `OC1M` writer - Output Compare 1 mode"]
136pub type OC1M_W<'a, const O: u8> =
137    crate::FieldWriterSafe<'a, u32, CCMR1_OUTPUT_SPEC, u8, OC1M_A, 3, O>;
138impl<'a, const O: u8> OC1M_W<'a, O> {
139    #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
140    #[inline(always)]
141    pub fn frozen(self) -> &'a mut W {
142        self.variant(OC1M_A::Frozen)
143    }
144    #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
145    #[inline(always)]
146    pub fn active_on_match(self) -> &'a mut W {
147        self.variant(OC1M_A::ActiveOnMatch)
148    }
149    #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
150    #[inline(always)]
151    pub fn inactive_on_match(self) -> &'a mut W {
152        self.variant(OC1M_A::InactiveOnMatch)
153    }
154    #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
155    #[inline(always)]
156    pub fn toggle(self) -> &'a mut W {
157        self.variant(OC1M_A::Toggle)
158    }
159    #[doc = "OCyREF is forced low"]
160    #[inline(always)]
161    pub fn force_inactive(self) -> &'a mut W {
162        self.variant(OC1M_A::ForceInactive)
163    }
164    #[doc = "OCyREF is forced high"]
165    #[inline(always)]
166    pub fn force_active(self) -> &'a mut W {
167        self.variant(OC1M_A::ForceActive)
168    }
169    #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
170    #[inline(always)]
171    pub fn pwm_mode1(self) -> &'a mut W {
172        self.variant(OC1M_A::PwmMode1)
173    }
174    #[doc = "Inversely to PwmMode1"]
175    #[inline(always)]
176    pub fn pwm_mode2(self) -> &'a mut W {
177        self.variant(OC1M_A::PwmMode2)
178    }
179}
180impl R {
181    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
182    #[inline(always)]
183    pub fn cc1s(&self) -> CC1S_R {
184        CC1S_R::new((self.bits & 3) as u8)
185    }
186    #[doc = "Bit 2 - Output compare 1 fast enable"]
187    #[inline(always)]
188    pub fn oc1fe(&self) -> OC1FE_R {
189        OC1FE_R::new(((self.bits >> 2) & 1) != 0)
190    }
191    #[doc = "Bit 3 - Output Compare 1 preload enable"]
192    #[inline(always)]
193    pub fn oc1pe(&self) -> OC1PE_R {
194        OC1PE_R::new(((self.bits >> 3) & 1) != 0)
195    }
196    #[doc = "Bits 4:6 - Output Compare 1 mode"]
197    #[inline(always)]
198    pub fn oc1m(&self) -> OC1M_R {
199        OC1M_R::new(((self.bits >> 4) & 7) as u8)
200    }
201}
202impl W {
203    #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
204    #[inline(always)]
205    pub fn cc1s(&mut self) -> CC1S_W<0> {
206        CC1S_W::new(self)
207    }
208    #[doc = "Bit 2 - Output compare 1 fast enable"]
209    #[inline(always)]
210    pub fn oc1fe(&mut self) -> OC1FE_W<2> {
211        OC1FE_W::new(self)
212    }
213    #[doc = "Bit 3 - Output Compare 1 preload enable"]
214    #[inline(always)]
215    pub fn oc1pe(&mut self) -> OC1PE_W<3> {
216        OC1PE_W::new(self)
217    }
218    #[doc = "Bits 4:6 - Output Compare 1 mode"]
219    #[inline(always)]
220    pub fn oc1m(&mut self) -> OC1M_W<4> {
221        OC1M_W::new(self)
222    }
223    #[doc = "Writes raw bits to the register."]
224    #[inline(always)]
225    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
226        self.0.bits(bits);
227        self
228    }
229}
230#[doc = "capture/compare mode register (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"]
231pub struct CCMR1_OUTPUT_SPEC;
232impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC {
233    type Ux = u32;
234}
235#[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"]
236impl crate::Readable for CCMR1_OUTPUT_SPEC {
237    type Reader = R;
238}
239#[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"]
240impl crate::Writable for CCMR1_OUTPUT_SPEC {
241    type Writer = W;
242}
243#[doc = "`reset()` method sets CCMR1_Output to value 0"]
244impl crate::Resettable for CCMR1_OUTPUT_SPEC {
245    #[inline(always)]
246    fn reset_value() -> Self::Ux {
247        0
248    }
249}
stm32f1/stm32f107/tim13/ccmr1_output.rs

stm32f1/stm32f107/tim13/
ccmr1_output.rs
