stm32f1/stm32f107/flash/
acr.rs

1#[doc = "Register `ACR` reader"]
2pub struct R(crate::R<ACR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ACR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ACR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ACR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ACR` writer"]
17pub struct W(crate::W<ACR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ACR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ACR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ACR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Latency\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum LATENCY_A {
41    #[doc = "0: Zero wait state, if 0 < SYSCLK≤ 24 MHz"]
42    Ws0 = 0,
43    #[doc = "1: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"]
44    Ws1 = 1,
45    #[doc = "2: Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"]
46    Ws2 = 2,
47}
48impl From<LATENCY_A> for u8 {
49    #[inline(always)]
50    fn from(variant: LATENCY_A) -> Self {
51        variant as _
52    }
53}
54#[doc = "Field `LATENCY` reader - Latency"]
55pub type LATENCY_R = crate::FieldReader<u8, LATENCY_A>;
56impl LATENCY_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<LATENCY_A> {
60        match self.bits {
61            0 => Some(LATENCY_A::Ws0),
62            1 => Some(LATENCY_A::Ws1),
63            2 => Some(LATENCY_A::Ws2),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `Ws0`"]
68    #[inline(always)]
69    pub fn is_ws0(&self) -> bool {
70        *self == LATENCY_A::Ws0
71    }
72    #[doc = "Checks if the value of the field is `Ws1`"]
73    #[inline(always)]
74    pub fn is_ws1(&self) -> bool {
75        *self == LATENCY_A::Ws1
76    }
77    #[doc = "Checks if the value of the field is `Ws2`"]
78    #[inline(always)]
79    pub fn is_ws2(&self) -> bool {
80        *self == LATENCY_A::Ws2
81    }
82}
83#[doc = "Field `LATENCY` writer - Latency"]
84pub type LATENCY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACR_SPEC, u8, LATENCY_A, 3, O>;
85impl<'a, const O: u8> LATENCY_W<'a, O> {
86    #[doc = "Zero wait state, if 0 < SYSCLK≤ 24 MHz"]
87    #[inline(always)]
88    pub fn ws0(self) -> &'a mut W {
89        self.variant(LATENCY_A::Ws0)
90    }
91    #[doc = "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"]
92    #[inline(always)]
93    pub fn ws1(self) -> &'a mut W {
94        self.variant(LATENCY_A::Ws1)
95    }
96    #[doc = "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"]
97    #[inline(always)]
98    pub fn ws2(self) -> &'a mut W {
99        self.variant(LATENCY_A::Ws2)
100    }
101}
102#[doc = "Field `HLFCYA` reader - Flash half cycle access enable"]
103pub type HLFCYA_R = crate::BitReader<bool>;
104#[doc = "Field `HLFCYA` writer - Flash half cycle access enable"]
105pub type HLFCYA_W<'a, const O: u8> = crate::BitWriter<'a, u32, ACR_SPEC, bool, O>;
106#[doc = "Field `PRFTBE` reader - Prefetch buffer enable"]
107pub type PRFTBE_R = crate::BitReader<bool>;
108#[doc = "Field `PRFTBE` writer - Prefetch buffer enable"]
109pub type PRFTBE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ACR_SPEC, bool, O>;
110#[doc = "Field `PRFTBS` reader - Prefetch buffer status"]
111pub type PRFTBS_R = crate::BitReader<bool>;
112impl R {
113    #[doc = "Bits 0:2 - Latency"]
114    #[inline(always)]
115    pub fn latency(&self) -> LATENCY_R {
116        LATENCY_R::new((self.bits & 7) as u8)
117    }
118    #[doc = "Bit 3 - Flash half cycle access enable"]
119    #[inline(always)]
120    pub fn hlfcya(&self) -> HLFCYA_R {
121        HLFCYA_R::new(((self.bits >> 3) & 1) != 0)
122    }
123    #[doc = "Bit 4 - Prefetch buffer enable"]
124    #[inline(always)]
125    pub fn prftbe(&self) -> PRFTBE_R {
126        PRFTBE_R::new(((self.bits >> 4) & 1) != 0)
127    }
128    #[doc = "Bit 5 - Prefetch buffer status"]
129    #[inline(always)]
130    pub fn prftbs(&self) -> PRFTBS_R {
131        PRFTBS_R::new(((self.bits >> 5) & 1) != 0)
132    }
133}
134impl W {
135    #[doc = "Bits 0:2 - Latency"]
136    #[inline(always)]
137    pub fn latency(&mut self) -> LATENCY_W<0> {
138        LATENCY_W::new(self)
139    }
140    #[doc = "Bit 3 - Flash half cycle access enable"]
141    #[inline(always)]
142    pub fn hlfcya(&mut self) -> HLFCYA_W<3> {
143        HLFCYA_W::new(self)
144    }
145    #[doc = "Bit 4 - Prefetch buffer enable"]
146    #[inline(always)]
147    pub fn prftbe(&mut self) -> PRFTBE_W<4> {
148        PRFTBE_W::new(self)
149    }
150    #[doc = "Writes raw bits to the register."]
151    #[inline(always)]
152    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
153        self.0.bits(bits);
154        self
155    }
156}
157#[doc = "Flash access control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acr](index.html) module"]
158pub struct ACR_SPEC;
159impl crate::RegisterSpec for ACR_SPEC {
160    type Ux = u32;
161}
162#[doc = "`read()` method returns [acr::R](R) reader structure"]
163impl crate::Readable for ACR_SPEC {
164    type Reader = R;
165}
166#[doc = "`write(|w| ..)` method takes [acr::W](W) writer structure"]
167impl crate::Writable for ACR_SPEC {
168    type Writer = W;
169}
170#[doc = "`reset()` method sets ACR to value 0x30"]
171impl crate::Resettable for ACR_SPEC {
172    #[inline(always)]
173    fn reset_value() -> Self::Ux {
174        0x30
175    }
176}
stm32f1/stm32f107/flash/acr.rs

stm32f1/stm32f107/flash/
acr.rs
