stm32f1/stm32f102/uart4/
sr.rs

1#[doc = "Register `SR` reader"]
2pub struct R(crate::R<SR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SR` writer"]
17pub struct W(crate::W<SR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PE` reader - Parity error"]
38pub type PE_R = crate::BitReader<bool>;
39#[doc = "Field `FE` reader - Framing error"]
40pub type FE_R = crate::BitReader<bool>;
41#[doc = "Field `NE` reader - Noise error flag"]
42pub type NE_R = crate::BitReader<bool>;
43#[doc = "Field `ORE` reader - Overrun error"]
44pub type ORE_R = crate::BitReader<bool>;
45#[doc = "Field `IDLE` reader - IDLE line detected"]
46pub type IDLE_R = crate::BitReader<bool>;
47#[doc = "Field `RXNE` reader - Read data register not empty"]
48pub type RXNE_R = crate::BitReader<bool>;
49#[doc = "Field `RXNE` writer - Read data register not empty"]
50pub type RXNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
51#[doc = "Field `TC` reader - Transmission complete"]
52pub type TC_R = crate::BitReader<bool>;
53#[doc = "Field `TC` writer - Transmission complete"]
54pub type TC_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
55#[doc = "Field `TXE` reader - Transmit data register empty"]
56pub type TXE_R = crate::BitReader<bool>;
57#[doc = "Field `LBD` reader - LIN break detection flag"]
58pub type LBD_R = crate::BitReader<bool>;
59#[doc = "Field `LBD` writer - LIN break detection flag"]
60pub type LBD_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
61impl R {
62    #[doc = "Bit 0 - Parity error"]
63    #[inline(always)]
64    pub fn pe(&self) -> PE_R {
65        PE_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1 - Framing error"]
68    #[inline(always)]
69    pub fn fe(&self) -> FE_R {
70        FE_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 2 - Noise error flag"]
73    #[inline(always)]
74    pub fn ne(&self) -> NE_R {
75        NE_R::new(((self.bits >> 2) & 1) != 0)
76    }
77    #[doc = "Bit 3 - Overrun error"]
78    #[inline(always)]
79    pub fn ore(&self) -> ORE_R {
80        ORE_R::new(((self.bits >> 3) & 1) != 0)
81    }
82    #[doc = "Bit 4 - IDLE line detected"]
83    #[inline(always)]
84    pub fn idle(&self) -> IDLE_R {
85        IDLE_R::new(((self.bits >> 4) & 1) != 0)
86    }
87    #[doc = "Bit 5 - Read data register not empty"]
88    #[inline(always)]
89    pub fn rxne(&self) -> RXNE_R {
90        RXNE_R::new(((self.bits >> 5) & 1) != 0)
91    }
92    #[doc = "Bit 6 - Transmission complete"]
93    #[inline(always)]
94    pub fn tc(&self) -> TC_R {
95        TC_R::new(((self.bits >> 6) & 1) != 0)
96    }
97    #[doc = "Bit 7 - Transmit data register empty"]
98    #[inline(always)]
99    pub fn txe(&self) -> TXE_R {
100        TXE_R::new(((self.bits >> 7) & 1) != 0)
101    }
102    #[doc = "Bit 8 - LIN break detection flag"]
103    #[inline(always)]
104    pub fn lbd(&self) -> LBD_R {
105        LBD_R::new(((self.bits >> 8) & 1) != 0)
106    }
107}
108impl W {
109    #[doc = "Bit 5 - Read data register not empty"]
110    #[inline(always)]
111    pub fn rxne(&mut self) -> RXNE_W<5> {
112        RXNE_W::new(self)
113    }
114    #[doc = "Bit 6 - Transmission complete"]
115    #[inline(always)]
116    pub fn tc(&mut self) -> TC_W<6> {
117        TC_W::new(self)
118    }
119    #[doc = "Bit 8 - LIN break detection flag"]
120    #[inline(always)]
121    pub fn lbd(&mut self) -> LBD_W<8> {
122        LBD_W::new(self)
123    }
124    #[doc = "Writes raw bits to the register."]
125    #[inline(always)]
126    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127        self.0.bits(bits);
128        self
129    }
130}
131#[doc = "Status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
132pub struct SR_SPEC;
133impl crate::RegisterSpec for SR_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [sr::R](R) reader structure"]
137impl crate::Readable for SR_SPEC {
138    type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
141impl crate::Writable for SR_SPEC {
142    type Writer = W;
143}
144#[doc = "`reset()` method sets SR to value 0"]
145impl crate::Resettable for SR_SPEC {
146    #[inline(always)]
147    fn reset_value() -> Self::Ux {
148        0
149    }
150}
stm32f1/stm32f102/uart4/sr.rs

stm32f1/stm32f102/uart4/
sr.rs
