stm32f1/stm32f101/tim2/
cr2.rs

1#[doc = "Register `CR2` reader"]
2pub struct R(crate::R<CR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CR2` writer"]
17pub struct W(crate::W<CR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "TI1 selection\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum TI1S_A {
40    #[doc = "0: The TIMx_CH1 pin is connected to TI1 input"]
41    Normal = 0,
42    #[doc = "1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
43    Xor = 1,
44}
45impl From<TI1S_A> for bool {
46    #[inline(always)]
47    fn from(variant: TI1S_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `TI1S` reader - TI1 selection"]
52pub type TI1S_R = crate::BitReader<TI1S_A>;
53impl TI1S_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> TI1S_A {
57        match self.bits {
58            false => TI1S_A::Normal,
59            true => TI1S_A::Xor,
60        }
61    }
62    #[doc = "Checks if the value of the field is `Normal`"]
63    #[inline(always)]
64    pub fn is_normal(&self) -> bool {
65        *self == TI1S_A::Normal
66    }
67    #[doc = "Checks if the value of the field is `Xor`"]
68    #[inline(always)]
69    pub fn is_xor(&self) -> bool {
70        *self == TI1S_A::Xor
71    }
72}
73#[doc = "Field `TI1S` writer - TI1 selection"]
74pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, TI1S_A, O>;
75impl<'a, const O: u8> TI1S_W<'a, O> {
76    #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
77    #[inline(always)]
78    pub fn normal(self) -> &'a mut W {
79        self.variant(TI1S_A::Normal)
80    }
81    #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
82    #[inline(always)]
83    pub fn xor(self) -> &'a mut W {
84        self.variant(TI1S_A::Xor)
85    }
86}
87#[doc = "Master mode selection\n\nValue on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq)]
89#[repr(u8)]
90pub enum MMS_A {
91    #[doc = "0: The UG bit from the TIMx_EGR register is used as trigger output"]
92    Reset = 0,
93    #[doc = "1: The counter enable signal, CNT_EN, is used as trigger output"]
94    Enable = 1,
95    #[doc = "2: The update event is selected as trigger output"]
96    Update = 2,
97    #[doc = "3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
98    ComparePulse = 3,
99    #[doc = "4: OC1REF signal is used as trigger output"]
100    CompareOc1 = 4,
101    #[doc = "5: OC2REF signal is used as trigger output"]
102    CompareOc2 = 5,
103    #[doc = "6: OC3REF signal is used as trigger output"]
104    CompareOc3 = 6,
105    #[doc = "7: OC4REF signal is used as trigger output"]
106    CompareOc4 = 7,
107}
108impl From<MMS_A> for u8 {
109    #[inline(always)]
110    fn from(variant: MMS_A) -> Self {
111        variant as _
112    }
113}
114#[doc = "Field `MMS` reader - Master mode selection"]
115pub type MMS_R = crate::FieldReader<u8, MMS_A>;
116impl MMS_R {
117    #[doc = "Get enumerated values variant"]
118    #[inline(always)]
119    pub fn variant(&self) -> MMS_A {
120        match self.bits {
121            0 => MMS_A::Reset,
122            1 => MMS_A::Enable,
123            2 => MMS_A::Update,
124            3 => MMS_A::ComparePulse,
125            4 => MMS_A::CompareOc1,
126            5 => MMS_A::CompareOc2,
127            6 => MMS_A::CompareOc3,
128            7 => MMS_A::CompareOc4,
129            _ => unreachable!(),
130        }
131    }
132    #[doc = "Checks if the value of the field is `Reset`"]
133    #[inline(always)]
134    pub fn is_reset(&self) -> bool {
135        *self == MMS_A::Reset
136    }
137    #[doc = "Checks if the value of the field is `Enable`"]
138    #[inline(always)]
139    pub fn is_enable(&self) -> bool {
140        *self == MMS_A::Enable
141    }
142    #[doc = "Checks if the value of the field is `Update`"]
143    #[inline(always)]
144    pub fn is_update(&self) -> bool {
145        *self == MMS_A::Update
146    }
147    #[doc = "Checks if the value of the field is `ComparePulse`"]
148    #[inline(always)]
149    pub fn is_compare_pulse(&self) -> bool {
150        *self == MMS_A::ComparePulse
151    }
152    #[doc = "Checks if the value of the field is `CompareOc1`"]
153    #[inline(always)]
154    pub fn is_compare_oc1(&self) -> bool {
155        *self == MMS_A::CompareOc1
156    }
157    #[doc = "Checks if the value of the field is `CompareOc2`"]
158    #[inline(always)]
159    pub fn is_compare_oc2(&self) -> bool {
160        *self == MMS_A::CompareOc2
161    }
162    #[doc = "Checks if the value of the field is `CompareOc3`"]
163    #[inline(always)]
164    pub fn is_compare_oc3(&self) -> bool {
165        *self == MMS_A::CompareOc3
166    }
167    #[doc = "Checks if the value of the field is `CompareOc4`"]
168    #[inline(always)]
169    pub fn is_compare_oc4(&self) -> bool {
170        *self == MMS_A::CompareOc4
171    }
172}
173#[doc = "Field `MMS` writer - Master mode selection"]
174pub type MMS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, MMS_A, 3, O>;
175impl<'a, const O: u8> MMS_W<'a, O> {
176    #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
177    #[inline(always)]
178    pub fn reset(self) -> &'a mut W {
179        self.variant(MMS_A::Reset)
180    }
181    #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
182    #[inline(always)]
183    pub fn enable(self) -> &'a mut W {
184        self.variant(MMS_A::Enable)
185    }
186    #[doc = "The update event is selected as trigger output"]
187    #[inline(always)]
188    pub fn update(self) -> &'a mut W {
189        self.variant(MMS_A::Update)
190    }
191    #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
192    #[inline(always)]
193    pub fn compare_pulse(self) -> &'a mut W {
194        self.variant(MMS_A::ComparePulse)
195    }
196    #[doc = "OC1REF signal is used as trigger output"]
197    #[inline(always)]
198    pub fn compare_oc1(self) -> &'a mut W {
199        self.variant(MMS_A::CompareOc1)
200    }
201    #[doc = "OC2REF signal is used as trigger output"]
202    #[inline(always)]
203    pub fn compare_oc2(self) -> &'a mut W {
204        self.variant(MMS_A::CompareOc2)
205    }
206    #[doc = "OC3REF signal is used as trigger output"]
207    #[inline(always)]
208    pub fn compare_oc3(self) -> &'a mut W {
209        self.variant(MMS_A::CompareOc3)
210    }
211    #[doc = "OC4REF signal is used as trigger output"]
212    #[inline(always)]
213    pub fn compare_oc4(self) -> &'a mut W {
214        self.variant(MMS_A::CompareOc4)
215    }
216}
217#[doc = "Capture/compare DMA selection\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq)]
219pub enum CCDS_A {
220    #[doc = "0: CCx DMA request sent when CCx event occurs"]
221    OnCompare = 0,
222    #[doc = "1: CCx DMA request sent when update event occurs"]
223    OnUpdate = 1,
224}
225impl From<CCDS_A> for bool {
226    #[inline(always)]
227    fn from(variant: CCDS_A) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `CCDS` reader - Capture/compare DMA selection"]
232pub type CCDS_R = crate::BitReader<CCDS_A>;
233impl CCDS_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub fn variant(&self) -> CCDS_A {
237        match self.bits {
238            false => CCDS_A::OnCompare,
239            true => CCDS_A::OnUpdate,
240        }
241    }
242    #[doc = "Checks if the value of the field is `OnCompare`"]
243    #[inline(always)]
244    pub fn is_on_compare(&self) -> bool {
245        *self == CCDS_A::OnCompare
246    }
247    #[doc = "Checks if the value of the field is `OnUpdate`"]
248    #[inline(always)]
249    pub fn is_on_update(&self) -> bool {
250        *self == CCDS_A::OnUpdate
251    }
252}
253#[doc = "Field `CCDS` writer - Capture/compare DMA selection"]
254pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, CCDS_A, O>;
255impl<'a, const O: u8> CCDS_W<'a, O> {
256    #[doc = "CCx DMA request sent when CCx event occurs"]
257    #[inline(always)]
258    pub fn on_compare(self) -> &'a mut W {
259        self.variant(CCDS_A::OnCompare)
260    }
261    #[doc = "CCx DMA request sent when update event occurs"]
262    #[inline(always)]
263    pub fn on_update(self) -> &'a mut W {
264        self.variant(CCDS_A::OnUpdate)
265    }
266}
267impl R {
268    #[doc = "Bit 7 - TI1 selection"]
269    #[inline(always)]
270    pub fn ti1s(&self) -> TI1S_R {
271        TI1S_R::new(((self.bits >> 7) & 1) != 0)
272    }
273    #[doc = "Bits 4:6 - Master mode selection"]
274    #[inline(always)]
275    pub fn mms(&self) -> MMS_R {
276        MMS_R::new(((self.bits >> 4) & 7) as u8)
277    }
278    #[doc = "Bit 3 - Capture/compare DMA selection"]
279    #[inline(always)]
280    pub fn ccds(&self) -> CCDS_R {
281        CCDS_R::new(((self.bits >> 3) & 1) != 0)
282    }
283}
284impl W {
285    #[doc = "Bit 7 - TI1 selection"]
286    #[inline(always)]
287    pub fn ti1s(&mut self) -> TI1S_W<7> {
288        TI1S_W::new(self)
289    }
290    #[doc = "Bits 4:6 - Master mode selection"]
291    #[inline(always)]
292    pub fn mms(&mut self) -> MMS_W<4> {
293        MMS_W::new(self)
294    }
295    #[doc = "Bit 3 - Capture/compare DMA selection"]
296    #[inline(always)]
297    pub fn ccds(&mut self) -> CCDS_W<3> {
298        CCDS_W::new(self)
299    }
300    #[doc = "Writes raw bits to the register."]
301    #[inline(always)]
302    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
303        self.0.bits(bits);
304        self
305    }
306}
307#[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"]
308pub struct CR2_SPEC;
309impl crate::RegisterSpec for CR2_SPEC {
310    type Ux = u32;
311}
312#[doc = "`read()` method returns [cr2::R](R) reader structure"]
313impl crate::Readable for CR2_SPEC {
314    type Reader = R;
315}
316#[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"]
317impl crate::Writable for CR2_SPEC {
318    type Writer = W;
319}
320#[doc = "`reset()` method sets CR2 to value 0"]
321impl crate::Resettable for CR2_SPEC {
322    #[inline(always)]
323    fn reset_value() -> Self::Ux {
324        0
325    }
326}
stm32f1/stm32f101/tim2/cr2.rs

stm32f1/stm32f101/tim2/
cr2.rs
