stm32f1/stm32f101/rtc/
divl.rs

1#[doc = "Register `DIVL` reader"]
2pub struct R(crate::R<DIVL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIVL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIVL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIVL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `DIVL` reader - RTC prescaler divider register Low"]
17pub type DIVL_R = crate::FieldReader<u16, u16>;
18impl R {
19    #[doc = "Bits 0:15 - RTC prescaler divider register Low"]
20    #[inline(always)]
21    pub fn divl(&self) -> DIVL_R {
22        DIVL_R::new((self.bits & 0xffff) as u16)
23    }
24}
25#[doc = "RTC Prescaler Divider Register Low\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divl](index.html) module"]
26pub struct DIVL_SPEC;
27impl crate::RegisterSpec for DIVL_SPEC {
28    type Ux = u32;
29}
30#[doc = "`read()` method returns [divl::R](R) reader structure"]
31impl crate::Readable for DIVL_SPEC {
32    type Reader = R;
33}
34#[doc = "`reset()` method sets DIVL to value 0x8000"]
35impl crate::Resettable for DIVL_SPEC {
36    #[inline(always)]
37    fn reset_value() -> Self::Ux {
38        0x8000
39    }
40}
stm32f1/stm32f101/rtc/divl.rs

stm32f1/stm32f101/rtc/
divl.rs
