stm32f1/stm32f101/rcc/
cfgr.rs

1#[doc = "Register `CFGR` reader"]
2pub struct R(crate::R<CFGR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFGR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFGR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFGR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFGR` writer"]
17pub struct W(crate::W<CFGR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFGR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFGR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFGR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "System clock Switch\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum SW_A {
41    #[doc = "0: HSI selected as system clock"]
42    Hsi = 0,
43    #[doc = "1: HSE selected as system clock"]
44    Hse = 1,
45    #[doc = "2: PLL selected as system clock"]
46    Pll = 2,
47}
48impl From<SW_A> for u8 {
49    #[inline(always)]
50    fn from(variant: SW_A) -> Self {
51        variant as _
52    }
53}
54#[doc = "Field `SW` reader - System clock Switch"]
55pub type SW_R = crate::FieldReader<u8, SW_A>;
56impl SW_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<SW_A> {
60        match self.bits {
61            0 => Some(SW_A::Hsi),
62            1 => Some(SW_A::Hse),
63            2 => Some(SW_A::Pll),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `Hsi`"]
68    #[inline(always)]
69    pub fn is_hsi(&self) -> bool {
70        *self == SW_A::Hsi
71    }
72    #[doc = "Checks if the value of the field is `Hse`"]
73    #[inline(always)]
74    pub fn is_hse(&self) -> bool {
75        *self == SW_A::Hse
76    }
77    #[doc = "Checks if the value of the field is `Pll`"]
78    #[inline(always)]
79    pub fn is_pll(&self) -> bool {
80        *self == SW_A::Pll
81    }
82}
83#[doc = "Field `SW` writer - System clock Switch"]
84pub type SW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, SW_A, 2, O>;
85impl<'a, const O: u8> SW_W<'a, O> {
86    #[doc = "HSI selected as system clock"]
87    #[inline(always)]
88    pub fn hsi(self) -> &'a mut W {
89        self.variant(SW_A::Hsi)
90    }
91    #[doc = "HSE selected as system clock"]
92    #[inline(always)]
93    pub fn hse(self) -> &'a mut W {
94        self.variant(SW_A::Hse)
95    }
96    #[doc = "PLL selected as system clock"]
97    #[inline(always)]
98    pub fn pll(self) -> &'a mut W {
99        self.variant(SW_A::Pll)
100    }
101}
102#[doc = "System Clock Switch Status\n\nValue on reset: 0"]
103#[derive(Clone, Copy, Debug, PartialEq)]
104#[repr(u8)]
105pub enum SWS_A {
106    #[doc = "0: HSI oscillator used as system clock"]
107    Hsi = 0,
108    #[doc = "1: HSE oscillator used as system clock"]
109    Hse = 1,
110    #[doc = "2: PLL used as system clock"]
111    Pll = 2,
112}
113impl From<SWS_A> for u8 {
114    #[inline(always)]
115    fn from(variant: SWS_A) -> Self {
116        variant as _
117    }
118}
119#[doc = "Field `SWS` reader - System Clock Switch Status"]
120pub type SWS_R = crate::FieldReader<u8, SWS_A>;
121impl SWS_R {
122    #[doc = "Get enumerated values variant"]
123    #[inline(always)]
124    pub fn variant(&self) -> Option<SWS_A> {
125        match self.bits {
126            0 => Some(SWS_A::Hsi),
127            1 => Some(SWS_A::Hse),
128            2 => Some(SWS_A::Pll),
129            _ => None,
130        }
131    }
132    #[doc = "Checks if the value of the field is `Hsi`"]
133    #[inline(always)]
134    pub fn is_hsi(&self) -> bool {
135        *self == SWS_A::Hsi
136    }
137    #[doc = "Checks if the value of the field is `Hse`"]
138    #[inline(always)]
139    pub fn is_hse(&self) -> bool {
140        *self == SWS_A::Hse
141    }
142    #[doc = "Checks if the value of the field is `Pll`"]
143    #[inline(always)]
144    pub fn is_pll(&self) -> bool {
145        *self == SWS_A::Pll
146    }
147}
148#[doc = "AHB prescaler\n\nValue on reset: 0"]
149#[derive(Clone, Copy, Debug, PartialEq)]
150#[repr(u8)]
151pub enum HPRE_A {
152    #[doc = "0: SYSCLK not divided"]
153    Div1 = 0,
154    #[doc = "8: SYSCLK divided by 2"]
155    Div2 = 8,
156    #[doc = "9: SYSCLK divided by 4"]
157    Div4 = 9,
158    #[doc = "10: SYSCLK divided by 8"]
159    Div8 = 10,
160    #[doc = "11: SYSCLK divided by 16"]
161    Div16 = 11,
162    #[doc = "12: SYSCLK divided by 64"]
163    Div64 = 12,
164    #[doc = "13: SYSCLK divided by 128"]
165    Div128 = 13,
166    #[doc = "14: SYSCLK divided by 256"]
167    Div256 = 14,
168    #[doc = "15: SYSCLK divided by 512"]
169    Div512 = 15,
170}
171impl From<HPRE_A> for u8 {
172    #[inline(always)]
173    fn from(variant: HPRE_A) -> Self {
174        variant as _
175    }
176}
177#[doc = "Field `HPRE` reader - AHB prescaler"]
178pub type HPRE_R = crate::FieldReader<u8, HPRE_A>;
179impl HPRE_R {
180    #[doc = "Get enumerated values variant"]
181    #[inline(always)]
182    pub fn variant(&self) -> Option<HPRE_A> {
183        match self.bits {
184            0 => Some(HPRE_A::Div1),
185            8 => Some(HPRE_A::Div2),
186            9 => Some(HPRE_A::Div4),
187            10 => Some(HPRE_A::Div8),
188            11 => Some(HPRE_A::Div16),
189            12 => Some(HPRE_A::Div64),
190            13 => Some(HPRE_A::Div128),
191            14 => Some(HPRE_A::Div256),
192            15 => Some(HPRE_A::Div512),
193            _ => None,
194        }
195    }
196    #[doc = "Checks if the value of the field is `Div1`"]
197    #[inline(always)]
198    pub fn is_div1(&self) -> bool {
199        *self == HPRE_A::Div1
200    }
201    #[doc = "Checks if the value of the field is `Div2`"]
202    #[inline(always)]
203    pub fn is_div2(&self) -> bool {
204        *self == HPRE_A::Div2
205    }
206    #[doc = "Checks if the value of the field is `Div4`"]
207    #[inline(always)]
208    pub fn is_div4(&self) -> bool {
209        *self == HPRE_A::Div4
210    }
211    #[doc = "Checks if the value of the field is `Div8`"]
212    #[inline(always)]
213    pub fn is_div8(&self) -> bool {
214        *self == HPRE_A::Div8
215    }
216    #[doc = "Checks if the value of the field is `Div16`"]
217    #[inline(always)]
218    pub fn is_div16(&self) -> bool {
219        *self == HPRE_A::Div16
220    }
221    #[doc = "Checks if the value of the field is `Div64`"]
222    #[inline(always)]
223    pub fn is_div64(&self) -> bool {
224        *self == HPRE_A::Div64
225    }
226    #[doc = "Checks if the value of the field is `Div128`"]
227    #[inline(always)]
228    pub fn is_div128(&self) -> bool {
229        *self == HPRE_A::Div128
230    }
231    #[doc = "Checks if the value of the field is `Div256`"]
232    #[inline(always)]
233    pub fn is_div256(&self) -> bool {
234        *self == HPRE_A::Div256
235    }
236    #[doc = "Checks if the value of the field is `Div512`"]
237    #[inline(always)]
238    pub fn is_div512(&self) -> bool {
239        *self == HPRE_A::Div512
240    }
241}
242#[doc = "Field `HPRE` writer - AHB prescaler"]
243pub type HPRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, HPRE_A, 4, O>;
244impl<'a, const O: u8> HPRE_W<'a, O> {
245    #[doc = "SYSCLK not divided"]
246    #[inline(always)]
247    pub fn div1(self) -> &'a mut W {
248        self.variant(HPRE_A::Div1)
249    }
250    #[doc = "SYSCLK divided by 2"]
251    #[inline(always)]
252    pub fn div2(self) -> &'a mut W {
253        self.variant(HPRE_A::Div2)
254    }
255    #[doc = "SYSCLK divided by 4"]
256    #[inline(always)]
257    pub fn div4(self) -> &'a mut W {
258        self.variant(HPRE_A::Div4)
259    }
260    #[doc = "SYSCLK divided by 8"]
261    #[inline(always)]
262    pub fn div8(self) -> &'a mut W {
263        self.variant(HPRE_A::Div8)
264    }
265    #[doc = "SYSCLK divided by 16"]
266    #[inline(always)]
267    pub fn div16(self) -> &'a mut W {
268        self.variant(HPRE_A::Div16)
269    }
270    #[doc = "SYSCLK divided by 64"]
271    #[inline(always)]
272    pub fn div64(self) -> &'a mut W {
273        self.variant(HPRE_A::Div64)
274    }
275    #[doc = "SYSCLK divided by 128"]
276    #[inline(always)]
277    pub fn div128(self) -> &'a mut W {
278        self.variant(HPRE_A::Div128)
279    }
280    #[doc = "SYSCLK divided by 256"]
281    #[inline(always)]
282    pub fn div256(self) -> &'a mut W {
283        self.variant(HPRE_A::Div256)
284    }
285    #[doc = "SYSCLK divided by 512"]
286    #[inline(always)]
287    pub fn div512(self) -> &'a mut W {
288        self.variant(HPRE_A::Div512)
289    }
290}
291#[doc = "APB Low speed prescaler (APB1)\n\nValue on reset: 0"]
292#[derive(Clone, Copy, Debug, PartialEq)]
293#[repr(u8)]
294pub enum PPRE1_A {
295    #[doc = "0: HCLK not divided"]
296    Div1 = 0,
297    #[doc = "4: HCLK divided by 2"]
298    Div2 = 4,
299    #[doc = "5: HCLK divided by 4"]
300    Div4 = 5,
301    #[doc = "6: HCLK divided by 8"]
302    Div8 = 6,
303    #[doc = "7: HCLK divided by 16"]
304    Div16 = 7,
305}
306impl From<PPRE1_A> for u8 {
307    #[inline(always)]
308    fn from(variant: PPRE1_A) -> Self {
309        variant as _
310    }
311}
312#[doc = "Field `PPRE1` reader - APB Low speed prescaler (APB1)"]
313pub type PPRE1_R = crate::FieldReader<u8, PPRE1_A>;
314impl PPRE1_R {
315    #[doc = "Get enumerated values variant"]
316    #[inline(always)]
317    pub fn variant(&self) -> Option<PPRE1_A> {
318        match self.bits {
319            0 => Some(PPRE1_A::Div1),
320            4 => Some(PPRE1_A::Div2),
321            5 => Some(PPRE1_A::Div4),
322            6 => Some(PPRE1_A::Div8),
323            7 => Some(PPRE1_A::Div16),
324            _ => None,
325        }
326    }
327    #[doc = "Checks if the value of the field is `Div1`"]
328    #[inline(always)]
329    pub fn is_div1(&self) -> bool {
330        *self == PPRE1_A::Div1
331    }
332    #[doc = "Checks if the value of the field is `Div2`"]
333    #[inline(always)]
334    pub fn is_div2(&self) -> bool {
335        *self == PPRE1_A::Div2
336    }
337    #[doc = "Checks if the value of the field is `Div4`"]
338    #[inline(always)]
339    pub fn is_div4(&self) -> bool {
340        *self == PPRE1_A::Div4
341    }
342    #[doc = "Checks if the value of the field is `Div8`"]
343    #[inline(always)]
344    pub fn is_div8(&self) -> bool {
345        *self == PPRE1_A::Div8
346    }
347    #[doc = "Checks if the value of the field is `Div16`"]
348    #[inline(always)]
349    pub fn is_div16(&self) -> bool {
350        *self == PPRE1_A::Div16
351    }
352}
353#[doc = "Field `PPRE1` writer - APB Low speed prescaler (APB1)"]
354pub type PPRE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, PPRE1_A, 3, O>;
355impl<'a, const O: u8> PPRE1_W<'a, O> {
356    #[doc = "HCLK not divided"]
357    #[inline(always)]
358    pub fn div1(self) -> &'a mut W {
359        self.variant(PPRE1_A::Div1)
360    }
361    #[doc = "HCLK divided by 2"]
362    #[inline(always)]
363    pub fn div2(self) -> &'a mut W {
364        self.variant(PPRE1_A::Div2)
365    }
366    #[doc = "HCLK divided by 4"]
367    #[inline(always)]
368    pub fn div4(self) -> &'a mut W {
369        self.variant(PPRE1_A::Div4)
370    }
371    #[doc = "HCLK divided by 8"]
372    #[inline(always)]
373    pub fn div8(self) -> &'a mut W {
374        self.variant(PPRE1_A::Div8)
375    }
376    #[doc = "HCLK divided by 16"]
377    #[inline(always)]
378    pub fn div16(self) -> &'a mut W {
379        self.variant(PPRE1_A::Div16)
380    }
381}
382#[doc = "APB High speed prescaler (APB2)"]
383pub use PPRE1_A as PPRE2_A;
384#[doc = "Field `PPRE2` reader - APB High speed prescaler (APB2)"]
385pub use PPRE1_R as PPRE2_R;
386#[doc = "Field `PPRE2` writer - APB High speed prescaler (APB2)"]
387pub use PPRE1_W as PPRE2_W;
388#[doc = "ADC prescaler\n\nValue on reset: 0"]
389#[derive(Clone, Copy, Debug, PartialEq)]
390#[repr(u8)]
391pub enum ADCPRE_A {
392    #[doc = "0: PCLK2 divided by 2"]
393    Div2 = 0,
394    #[doc = "1: PCLK2 divided by 4"]
395    Div4 = 1,
396    #[doc = "2: PCLK2 divided by 8"]
397    Div6 = 2,
398    #[doc = "3: PCLK2 divided by 16"]
399    Div8 = 3,
400}
401impl From<ADCPRE_A> for u8 {
402    #[inline(always)]
403    fn from(variant: ADCPRE_A) -> Self {
404        variant as _
405    }
406}
407#[doc = "Field `ADCPRE` reader - ADC prescaler"]
408pub type ADCPRE_R = crate::FieldReader<u8, ADCPRE_A>;
409impl ADCPRE_R {
410    #[doc = "Get enumerated values variant"]
411    #[inline(always)]
412    pub fn variant(&self) -> ADCPRE_A {
413        match self.bits {
414            0 => ADCPRE_A::Div2,
415            1 => ADCPRE_A::Div4,
416            2 => ADCPRE_A::Div6,
417            3 => ADCPRE_A::Div8,
418            _ => unreachable!(),
419        }
420    }
421    #[doc = "Checks if the value of the field is `Div2`"]
422    #[inline(always)]
423    pub fn is_div2(&self) -> bool {
424        *self == ADCPRE_A::Div2
425    }
426    #[doc = "Checks if the value of the field is `Div4`"]
427    #[inline(always)]
428    pub fn is_div4(&self) -> bool {
429        *self == ADCPRE_A::Div4
430    }
431    #[doc = "Checks if the value of the field is `Div6`"]
432    #[inline(always)]
433    pub fn is_div6(&self) -> bool {
434        *self == ADCPRE_A::Div6
435    }
436    #[doc = "Checks if the value of the field is `Div8`"]
437    #[inline(always)]
438    pub fn is_div8(&self) -> bool {
439        *self == ADCPRE_A::Div8
440    }
441}
442#[doc = "Field `ADCPRE` writer - ADC prescaler"]
443pub type ADCPRE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CFGR_SPEC, u8, ADCPRE_A, 2, O>;
444impl<'a, const O: u8> ADCPRE_W<'a, O> {
445    #[doc = "PCLK2 divided by 2"]
446    #[inline(always)]
447    pub fn div2(self) -> &'a mut W {
448        self.variant(ADCPRE_A::Div2)
449    }
450    #[doc = "PCLK2 divided by 4"]
451    #[inline(always)]
452    pub fn div4(self) -> &'a mut W {
453        self.variant(ADCPRE_A::Div4)
454    }
455    #[doc = "PCLK2 divided by 8"]
456    #[inline(always)]
457    pub fn div6(self) -> &'a mut W {
458        self.variant(ADCPRE_A::Div6)
459    }
460    #[doc = "PCLK2 divided by 16"]
461    #[inline(always)]
462    pub fn div8(self) -> &'a mut W {
463        self.variant(ADCPRE_A::Div8)
464    }
465}
466#[doc = "PLL entry clock source\n\nValue on reset: 0"]
467#[derive(Clone, Copy, Debug, PartialEq)]
468pub enum PLLSRC_A {
469    #[doc = "0: HSI divided by 2 selected as PLL input clock"]
470    HsiDiv2 = 0,
471    #[doc = "1: HSE divided by PREDIV selected as PLL input clock"]
472    HseDivPrediv = 1,
473}
474impl From<PLLSRC_A> for bool {
475    #[inline(always)]
476    fn from(variant: PLLSRC_A) -> Self {
477        variant as u8 != 0
478    }
479}
480#[doc = "Field `PLLSRC` reader - PLL entry clock source"]
481pub type PLLSRC_R = crate::BitReader<PLLSRC_A>;
482impl PLLSRC_R {
483    #[doc = "Get enumerated values variant"]
484    #[inline(always)]
485    pub fn variant(&self) -> PLLSRC_A {
486        match self.bits {
487            false => PLLSRC_A::HsiDiv2,
488            true => PLLSRC_A::HseDivPrediv,
489        }
490    }
491    #[doc = "Checks if the value of the field is `HsiDiv2`"]
492    #[inline(always)]
493    pub fn is_hsi_div2(&self) -> bool {
494        *self == PLLSRC_A::HsiDiv2
495    }
496    #[doc = "Checks if the value of the field is `HseDivPrediv`"]
497    #[inline(always)]
498    pub fn is_hse_div_prediv(&self) -> bool {
499        *self == PLLSRC_A::HseDivPrediv
500    }
501}
502#[doc = "Field `PLLSRC` writer - PLL entry clock source"]
503pub type PLLSRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, PLLSRC_A, O>;
504impl<'a, const O: u8> PLLSRC_W<'a, O> {
505    #[doc = "HSI divided by 2 selected as PLL input clock"]
506    #[inline(always)]
507    pub fn hsi_div2(self) -> &'a mut W {
508        self.variant(PLLSRC_A::HsiDiv2)
509    }
510    #[doc = "HSE divided by PREDIV selected as PLL input clock"]
511    #[inline(always)]
512    pub fn hse_div_prediv(self) -> &'a mut W {
513        self.variant(PLLSRC_A::HseDivPrediv)
514    }
515}
516#[doc = "HSE divider for PLL entry\n\nValue on reset: 0"]
517#[derive(Clone, Copy, Debug, PartialEq)]
518pub enum PLLXTPRE_A {
519    #[doc = "0: HSE clock not divided"]
520    Div1 = 0,
521    #[doc = "1: HSE clock divided by 2"]
522    Div2 = 1,
523}
524impl From<PLLXTPRE_A> for bool {
525    #[inline(always)]
526    fn from(variant: PLLXTPRE_A) -> Self {
527        variant as u8 != 0
528    }
529}
530#[doc = "Field `PLLXTPRE` reader - HSE divider for PLL entry"]
531pub type PLLXTPRE_R = crate::BitReader<PLLXTPRE_A>;
532impl PLLXTPRE_R {
533    #[doc = "Get enumerated values variant"]
534    #[inline(always)]
535    pub fn variant(&self) -> PLLXTPRE_A {
536        match self.bits {
537            false => PLLXTPRE_A::Div1,
538            true => PLLXTPRE_A::Div2,
539        }
540    }
541    #[doc = "Checks if the value of the field is `Div1`"]
542    #[inline(always)]
543    pub fn is_div1(&self) -> bool {
544        *self == PLLXTPRE_A::Div1
545    }
546    #[doc = "Checks if the value of the field is `Div2`"]
547    #[inline(always)]
548    pub fn is_div2(&self) -> bool {
549        *self == PLLXTPRE_A::Div2
550    }
551}
552#[doc = "Field `PLLXTPRE` writer - HSE divider for PLL entry"]
553pub type PLLXTPRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, PLLXTPRE_A, O>;
554impl<'a, const O: u8> PLLXTPRE_W<'a, O> {
555    #[doc = "HSE clock not divided"]
556    #[inline(always)]
557    pub fn div1(self) -> &'a mut W {
558        self.variant(PLLXTPRE_A::Div1)
559    }
560    #[doc = "HSE clock divided by 2"]
561    #[inline(always)]
562    pub fn div2(self) -> &'a mut W {
563        self.variant(PLLXTPRE_A::Div2)
564    }
565}
566#[doc = "PLL Multiplication Factor\n\nValue on reset: 0"]
567#[derive(Clone, Copy, Debug, PartialEq)]
568#[repr(u8)]
569pub enum PLLMUL_A {
570    #[doc = "0: PLL input clock x2"]
571    Mul2 = 0,
572    #[doc = "1: PLL input clock x3"]
573    Mul3 = 1,
574    #[doc = "2: PLL input clock x4"]
575    Mul4 = 2,
576    #[doc = "3: PLL input clock x5"]
577    Mul5 = 3,
578    #[doc = "4: PLL input clock x6"]
579    Mul6 = 4,
580    #[doc = "5: PLL input clock x7"]
581    Mul7 = 5,
582    #[doc = "6: PLL input clock x8"]
583    Mul8 = 6,
584    #[doc = "7: PLL input clock x9"]
585    Mul9 = 7,
586    #[doc = "8: PLL input clock x10"]
587    Mul10 = 8,
588    #[doc = "9: PLL input clock x11"]
589    Mul11 = 9,
590    #[doc = "10: PLL input clock x12"]
591    Mul12 = 10,
592    #[doc = "11: PLL input clock x13"]
593    Mul13 = 11,
594    #[doc = "12: PLL input clock x14"]
595    Mul14 = 12,
596    #[doc = "13: PLL input clock x15"]
597    Mul15 = 13,
598    #[doc = "14: PLL input clock x16"]
599    Mul16 = 14,
600    #[doc = "15: PLL input clock x16"]
601    Mul16x = 15,
602}
603impl From<PLLMUL_A> for u8 {
604    #[inline(always)]
605    fn from(variant: PLLMUL_A) -> Self {
606        variant as _
607    }
608}
609#[doc = "Field `PLLMUL` reader - PLL Multiplication Factor"]
610pub type PLLMUL_R = crate::FieldReader<u8, PLLMUL_A>;
611impl PLLMUL_R {
612    #[doc = "Get enumerated values variant"]
613    #[inline(always)]
614    pub fn variant(&self) -> PLLMUL_A {
615        match self.bits {
616            0 => PLLMUL_A::Mul2,
617            1 => PLLMUL_A::Mul3,
618            2 => PLLMUL_A::Mul4,
619            3 => PLLMUL_A::Mul5,
620            4 => PLLMUL_A::Mul6,
621            5 => PLLMUL_A::Mul7,
622            6 => PLLMUL_A::Mul8,
623            7 => PLLMUL_A::Mul9,
624            8 => PLLMUL_A::Mul10,
625            9 => PLLMUL_A::Mul11,
626            10 => PLLMUL_A::Mul12,
627            11 => PLLMUL_A::Mul13,
628            12 => PLLMUL_A::Mul14,
629            13 => PLLMUL_A::Mul15,
630            14 => PLLMUL_A::Mul16,
631            15 => PLLMUL_A::Mul16x,
632            _ => unreachable!(),
633        }
634    }
635    #[doc = "Checks if the value of the field is `Mul2`"]
636    #[inline(always)]
637    pub fn is_mul2(&self) -> bool {
638        *self == PLLMUL_A::Mul2
639    }
640    #[doc = "Checks if the value of the field is `Mul3`"]
641    #[inline(always)]
642    pub fn is_mul3(&self) -> bool {
643        *self == PLLMUL_A::Mul3
644    }
645    #[doc = "Checks if the value of the field is `Mul4`"]
646    #[inline(always)]
647    pub fn is_mul4(&self) -> bool {
648        *self == PLLMUL_A::Mul4
649    }
650    #[doc = "Checks if the value of the field is `Mul5`"]
651    #[inline(always)]
652    pub fn is_mul5(&self) -> bool {
653        *self == PLLMUL_A::Mul5
654    }
655    #[doc = "Checks if the value of the field is `Mul6`"]
656    #[inline(always)]
657    pub fn is_mul6(&self) -> bool {
658        *self == PLLMUL_A::Mul6
659    }
660    #[doc = "Checks if the value of the field is `Mul7`"]
661    #[inline(always)]
662    pub fn is_mul7(&self) -> bool {
663        *self == PLLMUL_A::Mul7
664    }
665    #[doc = "Checks if the value of the field is `Mul8`"]
666    #[inline(always)]
667    pub fn is_mul8(&self) -> bool {
668        *self == PLLMUL_A::Mul8
669    }
670    #[doc = "Checks if the value of the field is `Mul9`"]
671    #[inline(always)]
672    pub fn is_mul9(&self) -> bool {
673        *self == PLLMUL_A::Mul9
674    }
675    #[doc = "Checks if the value of the field is `Mul10`"]
676    #[inline(always)]
677    pub fn is_mul10(&self) -> bool {
678        *self == PLLMUL_A::Mul10
679    }
680    #[doc = "Checks if the value of the field is `Mul11`"]
681    #[inline(always)]
682    pub fn is_mul11(&self) -> bool {
683        *self == PLLMUL_A::Mul11
684    }
685    #[doc = "Checks if the value of the field is `Mul12`"]
686    #[inline(always)]
687    pub fn is_mul12(&self) -> bool {
688        *self == PLLMUL_A::Mul12
689    }
690    #[doc = "Checks if the value of the field is `Mul13`"]
691    #[inline(always)]
692    pub fn is_mul13(&self) -> bool {
693        *self == PLLMUL_A::Mul13
694    }
695    #[doc = "Checks if the value of the field is `Mul14`"]
696    #[inline(always)]
697    pub fn is_mul14(&self) -> bool {
698        *self == PLLMUL_A::Mul14
699    }
700    #[doc = "Checks if the value of the field is `Mul15`"]
701    #[inline(always)]
702    pub fn is_mul15(&self) -> bool {
703        *self == PLLMUL_A::Mul15
704    }
705    #[doc = "Checks if the value of the field is `Mul16`"]
706    #[inline(always)]
707    pub fn is_mul16(&self) -> bool {
708        *self == PLLMUL_A::Mul16
709    }
710    #[doc = "Checks if the value of the field is `Mul16x`"]
711    #[inline(always)]
712    pub fn is_mul16x(&self) -> bool {
713        *self == PLLMUL_A::Mul16x
714    }
715}
716#[doc = "Field `PLLMUL` writer - PLL Multiplication Factor"]
717pub type PLLMUL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CFGR_SPEC, u8, PLLMUL_A, 4, O>;
718impl<'a, const O: u8> PLLMUL_W<'a, O> {
719    #[doc = "PLL input clock x2"]
720    #[inline(always)]
721    pub fn mul2(self) -> &'a mut W {
722        self.variant(PLLMUL_A::Mul2)
723    }
724    #[doc = "PLL input clock x3"]
725    #[inline(always)]
726    pub fn mul3(self) -> &'a mut W {
727        self.variant(PLLMUL_A::Mul3)
728    }
729    #[doc = "PLL input clock x4"]
730    #[inline(always)]
731    pub fn mul4(self) -> &'a mut W {
732        self.variant(PLLMUL_A::Mul4)
733    }
734    #[doc = "PLL input clock x5"]
735    #[inline(always)]
736    pub fn mul5(self) -> &'a mut W {
737        self.variant(PLLMUL_A::Mul5)
738    }
739    #[doc = "PLL input clock x6"]
740    #[inline(always)]
741    pub fn mul6(self) -> &'a mut W {
742        self.variant(PLLMUL_A::Mul6)
743    }
744    #[doc = "PLL input clock x7"]
745    #[inline(always)]
746    pub fn mul7(self) -> &'a mut W {
747        self.variant(PLLMUL_A::Mul7)
748    }
749    #[doc = "PLL input clock x8"]
750    #[inline(always)]
751    pub fn mul8(self) -> &'a mut W {
752        self.variant(PLLMUL_A::Mul8)
753    }
754    #[doc = "PLL input clock x9"]
755    #[inline(always)]
756    pub fn mul9(self) -> &'a mut W {
757        self.variant(PLLMUL_A::Mul9)
758    }
759    #[doc = "PLL input clock x10"]
760    #[inline(always)]
761    pub fn mul10(self) -> &'a mut W {
762        self.variant(PLLMUL_A::Mul10)
763    }
764    #[doc = "PLL input clock x11"]
765    #[inline(always)]
766    pub fn mul11(self) -> &'a mut W {
767        self.variant(PLLMUL_A::Mul11)
768    }
769    #[doc = "PLL input clock x12"]
770    #[inline(always)]
771    pub fn mul12(self) -> &'a mut W {
772        self.variant(PLLMUL_A::Mul12)
773    }
774    #[doc = "PLL input clock x13"]
775    #[inline(always)]
776    pub fn mul13(self) -> &'a mut W {
777        self.variant(PLLMUL_A::Mul13)
778    }
779    #[doc = "PLL input clock x14"]
780    #[inline(always)]
781    pub fn mul14(self) -> &'a mut W {
782        self.variant(PLLMUL_A::Mul14)
783    }
784    #[doc = "PLL input clock x15"]
785    #[inline(always)]
786    pub fn mul15(self) -> &'a mut W {
787        self.variant(PLLMUL_A::Mul15)
788    }
789    #[doc = "PLL input clock x16"]
790    #[inline(always)]
791    pub fn mul16(self) -> &'a mut W {
792        self.variant(PLLMUL_A::Mul16)
793    }
794    #[doc = "PLL input clock x16"]
795    #[inline(always)]
796    pub fn mul16x(self) -> &'a mut W {
797        self.variant(PLLMUL_A::Mul16x)
798    }
799}
800#[doc = "Microcontroller clock output\n\nValue on reset: 0"]
801#[derive(Clone, Copy, Debug, PartialEq)]
802#[repr(u8)]
803pub enum MCO_A {
804    #[doc = "0: MCO output disabled, no clock on MCO"]
805    NoMco = 0,
806    #[doc = "4: System clock selected"]
807    Sysclk = 4,
808    #[doc = "5: HSI oscillator clock selected"]
809    Hsi = 5,
810    #[doc = "6: HSE oscillator clock selected"]
811    Hse = 6,
812    #[doc = "7: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"]
813    Pll = 7,
814}
815impl From<MCO_A> for u8 {
816    #[inline(always)]
817    fn from(variant: MCO_A) -> Self {
818        variant as _
819    }
820}
821#[doc = "Field `MCO` reader - Microcontroller clock output"]
822pub type MCO_R = crate::FieldReader<u8, MCO_A>;
823impl MCO_R {
824    #[doc = "Get enumerated values variant"]
825    #[inline(always)]
826    pub fn variant(&self) -> Option<MCO_A> {
827        match self.bits {
828            0 => Some(MCO_A::NoMco),
829            4 => Some(MCO_A::Sysclk),
830            5 => Some(MCO_A::Hsi),
831            6 => Some(MCO_A::Hse),
832            7 => Some(MCO_A::Pll),
833            _ => None,
834        }
835    }
836    #[doc = "Checks if the value of the field is `NoMco`"]
837    #[inline(always)]
838    pub fn is_no_mco(&self) -> bool {
839        *self == MCO_A::NoMco
840    }
841    #[doc = "Checks if the value of the field is `Sysclk`"]
842    #[inline(always)]
843    pub fn is_sysclk(&self) -> bool {
844        *self == MCO_A::Sysclk
845    }
846    #[doc = "Checks if the value of the field is `Hsi`"]
847    #[inline(always)]
848    pub fn is_hsi(&self) -> bool {
849        *self == MCO_A::Hsi
850    }
851    #[doc = "Checks if the value of the field is `Hse`"]
852    #[inline(always)]
853    pub fn is_hse(&self) -> bool {
854        *self == MCO_A::Hse
855    }
856    #[doc = "Checks if the value of the field is `Pll`"]
857    #[inline(always)]
858    pub fn is_pll(&self) -> bool {
859        *self == MCO_A::Pll
860    }
861}
862#[doc = "Field `MCO` writer - Microcontroller clock output"]
863pub type MCO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, MCO_A, 3, O>;
864impl<'a, const O: u8> MCO_W<'a, O> {
865    #[doc = "MCO output disabled, no clock on MCO"]
866    #[inline(always)]
867    pub fn no_mco(self) -> &'a mut W {
868        self.variant(MCO_A::NoMco)
869    }
870    #[doc = "System clock selected"]
871    #[inline(always)]
872    pub fn sysclk(self) -> &'a mut W {
873        self.variant(MCO_A::Sysclk)
874    }
875    #[doc = "HSI oscillator clock selected"]
876    #[inline(always)]
877    pub fn hsi(self) -> &'a mut W {
878        self.variant(MCO_A::Hsi)
879    }
880    #[doc = "HSE oscillator clock selected"]
881    #[inline(always)]
882    pub fn hse(self) -> &'a mut W {
883        self.variant(MCO_A::Hse)
884    }
885    #[doc = "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"]
886    #[inline(always)]
887    pub fn pll(self) -> &'a mut W {
888        self.variant(MCO_A::Pll)
889    }
890}
891impl R {
892    #[doc = "Bits 0:1 - System clock Switch"]
893    #[inline(always)]
894    pub fn sw(&self) -> SW_R {
895        SW_R::new((self.bits & 3) as u8)
896    }
897    #[doc = "Bits 2:3 - System Clock Switch Status"]
898    #[inline(always)]
899    pub fn sws(&self) -> SWS_R {
900        SWS_R::new(((self.bits >> 2) & 3) as u8)
901    }
902    #[doc = "Bits 4:7 - AHB prescaler"]
903    #[inline(always)]
904    pub fn hpre(&self) -> HPRE_R {
905        HPRE_R::new(((self.bits >> 4) & 0x0f) as u8)
906    }
907    #[doc = "Bits 8:10 - APB Low speed prescaler (APB1)"]
908    #[inline(always)]
909    pub fn ppre1(&self) -> PPRE1_R {
910        PPRE1_R::new(((self.bits >> 8) & 7) as u8)
911    }
912    #[doc = "Bits 11:13 - APB High speed prescaler (APB2)"]
913    #[inline(always)]
914    pub fn ppre2(&self) -> PPRE2_R {
915        PPRE2_R::new(((self.bits >> 11) & 7) as u8)
916    }
917    #[doc = "Bits 14:15 - ADC prescaler"]
918    #[inline(always)]
919    pub fn adcpre(&self) -> ADCPRE_R {
920        ADCPRE_R::new(((self.bits >> 14) & 3) as u8)
921    }
922    #[doc = "Bit 16 - PLL entry clock source"]
923    #[inline(always)]
924    pub fn pllsrc(&self) -> PLLSRC_R {
925        PLLSRC_R::new(((self.bits >> 16) & 1) != 0)
926    }
927    #[doc = "Bit 17 - HSE divider for PLL entry"]
928    #[inline(always)]
929    pub fn pllxtpre(&self) -> PLLXTPRE_R {
930        PLLXTPRE_R::new(((self.bits >> 17) & 1) != 0)
931    }
932    #[doc = "Bits 18:21 - PLL Multiplication Factor"]
933    #[inline(always)]
934    pub fn pllmul(&self) -> PLLMUL_R {
935        PLLMUL_R::new(((self.bits >> 18) & 0x0f) as u8)
936    }
937    #[doc = "Bits 24:26 - Microcontroller clock output"]
938    #[inline(always)]
939    pub fn mco(&self) -> MCO_R {
940        MCO_R::new(((self.bits >> 24) & 7) as u8)
941    }
942}
943impl W {
944    #[doc = "Bits 0:1 - System clock Switch"]
945    #[inline(always)]
946    pub fn sw(&mut self) -> SW_W<0> {
947        SW_W::new(self)
948    }
949    #[doc = "Bits 4:7 - AHB prescaler"]
950    #[inline(always)]
951    pub fn hpre(&mut self) -> HPRE_W<4> {
952        HPRE_W::new(self)
953    }
954    #[doc = "Bits 8:10 - APB Low speed prescaler (APB1)"]
955    #[inline(always)]
956    pub fn ppre1(&mut self) -> PPRE1_W<8> {
957        PPRE1_W::new(self)
958    }
959    #[doc = "Bits 11:13 - APB High speed prescaler (APB2)"]
960    #[inline(always)]
961    pub fn ppre2(&mut self) -> PPRE2_W<11> {
962        PPRE2_W::new(self)
963    }
964    #[doc = "Bits 14:15 - ADC prescaler"]
965    #[inline(always)]
966    pub fn adcpre(&mut self) -> ADCPRE_W<14> {
967        ADCPRE_W::new(self)
968    }
969    #[doc = "Bit 16 - PLL entry clock source"]
970    #[inline(always)]
971    pub fn pllsrc(&mut self) -> PLLSRC_W<16> {
972        PLLSRC_W::new(self)
973    }
974    #[doc = "Bit 17 - HSE divider for PLL entry"]
975    #[inline(always)]
976    pub fn pllxtpre(&mut self) -> PLLXTPRE_W<17> {
977        PLLXTPRE_W::new(self)
978    }
979    #[doc = "Bits 18:21 - PLL Multiplication Factor"]
980    #[inline(always)]
981    pub fn pllmul(&mut self) -> PLLMUL_W<18> {
982        PLLMUL_W::new(self)
983    }
984    #[doc = "Bits 24:26 - Microcontroller clock output"]
985    #[inline(always)]
986    pub fn mco(&mut self) -> MCO_W<24> {
987        MCO_W::new(self)
988    }
989    #[doc = "Writes raw bits to the register."]
990    #[inline(always)]
991    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
992        self.0.bits(bits);
993        self
994    }
995}
996#[doc = "Clock configuration register (RCC_CFGR)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr](index.html) module"]
997pub struct CFGR_SPEC;
998impl crate::RegisterSpec for CFGR_SPEC {
999    type Ux = u32;
1000}
1001#[doc = "`read()` method returns [cfgr::R](R) reader structure"]
1002impl crate::Readable for CFGR_SPEC {
1003    type Reader = R;
1004}
1005#[doc = "`write(|w| ..)` method takes [cfgr::W](W) writer structure"]
1006impl crate::Writable for CFGR_SPEC {
1007    type Writer = W;
1008}
1009#[doc = "`reset()` method sets CFGR to value 0"]
1010impl crate::Resettable for CFGR_SPEC {
1011    #[inline(always)]
1012    fn reset_value() -> Self::Ux {
1013        0
1014    }
1015}
stm32f1/stm32f101/rcc/cfgr.rs

stm32f1/stm32f101/rcc/
cfgr.rs
