Struct stm32f1::stm32f103::dac::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub cr: CR,
    pub swtrigr: SWTRIGR,
    pub dhr12r1: DHR12R1,
    pub dhr12l1: DHR12L1,
    pub dhr8r1: DHR8R1,
    pub dhr12r2: DHR12R2,
    pub dhr12l2: DHR12L2,
    pub dhr8r2: DHR8R2,
    pub dhr12rd: DHR12RD,
    pub dhr12ld: DHR12LD,
    pub dhr8rd: DHR8RD,
    pub dor1: DOR1,
    pub dor2: DOR2,
}

Register block

Fields

cr: CR

0x00 - Control register (DAC_CR)

swtrigr: SWTRIGR

0x04 - DAC software trigger register (DAC_SWTRIGR)

dhr12r1: DHR12R1

0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

dhr12l1: DHR12L1

0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

dhr8r1: DHR8R1

0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

dhr12r2: DHR12R2

0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

dhr12l2: DHR12L2

0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

dhr8r2: DHR8R2

0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

dhr12rd: DHR12RD

0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

dhr12ld: DHR12LD

0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

dhr8rd: DHR8RD

0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

dor1: DOR1

0x2c - DAC channel1 data output register (DAC_DOR1)

dor2: DOR2

0x30 - DAC channel2 data output register (DAC_DOR2)

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