Enum stm32f1::stm32f102::rcc::cfgr::PLLSRC_A

pub enum PLLSRC_A {
    HSI_DIV2,
    HSE_DIV_PREDIV,
}

PLL entry clock source

Value on reset: 0

Variants

HSI_DIV2

0: HSI divided by 2 selected as PLL input clock

HSE_DIV_PREDIV

1: HSE divided by PREDIV selected as PLL input clock

Trait Implementations

impl Clone for PLLSRC_A

fn clone(&self) -> PLLSRC_A

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PLLSRC_A

impl Debug for PLLSRC_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq<PLLSRC_A> for PLLSRC_A

fn eq(&self, other: &PLLSRC_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]pub fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for PLLSRC_A