1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
#[doc = "Reader of register CCMR1_Output"] pub type R = crate::R<u32, super::CCMR1_OUTPUT>; #[doc = "Writer for register CCMR1_Output"] pub type W = crate::W<u32, super::CCMR1_OUTPUT>; #[doc = "Register CCMR1_Output `reset()`'s with value 0"] impl crate::ResetValue for super::CCMR1_OUTPUT { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `OC1M`"] pub type OC1M_R = crate::R<u8, u8>; #[doc = "Write proxy for field `OC1M`"] pub struct OC1M_W<'a> { w: &'a mut W, } impl<'a> OC1M_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4); self.w } } #[doc = "Reader of field `OC1PE`"] pub type OC1PE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `OC1PE`"] pub struct OC1PE_W<'a> { w: &'a mut W, } impl<'a> OC1PE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `CC1S`"] pub type CC1S_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CC1S`"] pub struct CC1S_W<'a> { w: &'a mut W, } impl<'a> CC1S_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); self.w } } impl R { #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] pub fn oc1m(&self) -> OC1M_R { OC1M_R::new(((self.bits >> 4) & 0x07) as u8) } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] pub fn oc1pe(&self) -> OC1PE_R { OC1PE_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&self) -> CC1S_R { CC1S_R::new((self.bits & 0x03) as u8) } } impl W { #[doc = "Bits 4:6 - Output Compare 1 mode"] #[inline(always)] pub fn oc1m(&mut self) -> OC1M_W { OC1M_W { w: self } } #[doc = "Bit 3 - Output Compare 1 preload enable"] #[inline(always)] pub fn oc1pe(&mut self) -> OC1PE_W { OC1PE_W { w: self } } #[doc = "Bits 0:1 - Capture/Compare 1 selection"] #[inline(always)] pub fn cc1s(&mut self) -> CC1S_W { CC1S_W { w: self } } }