stm32f1_staging/stm32f107/spi1/
i2scfgr.rs

1///Register `I2SCFGR` reader
2pub type R = crate::R<I2SCFGRrs>;
3///Register `I2SCFGR` writer
4pub type W = crate::W<I2SCFGRrs>;
5/**Channel length (number of bits per audio channel)
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CHLEN {
11    ///0: 16-bit wide
12    SixteenBit = 0,
13    ///1: 32-bit wide
14    ThirtyTwoBit = 1,
15}
16impl From<CHLEN> for bool {
17    #[inline(always)]
18    fn from(variant: CHLEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CHLEN` reader - Channel length (number of bits per audio channel)
23pub type CHLEN_R = crate::BitReader<CHLEN>;
24impl CHLEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CHLEN {
28        match self.bits {
29            false => CHLEN::SixteenBit,
30            true => CHLEN::ThirtyTwoBit,
31        }
32    }
33    ///16-bit wide
34    #[inline(always)]
35    pub fn is_sixteen_bit(&self) -> bool {
36        *self == CHLEN::SixteenBit
37    }
38    ///32-bit wide
39    #[inline(always)]
40    pub fn is_thirty_two_bit(&self) -> bool {
41        *self == CHLEN::ThirtyTwoBit
42    }
43}
44///Field `CHLEN` writer - Channel length (number of bits per audio channel)
45pub type CHLEN_W<'a, REG> = crate::BitWriter<'a, REG, CHLEN>;
46impl<'a, REG> CHLEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///16-bit wide
51    #[inline(always)]
52    pub fn sixteen_bit(self) -> &'a mut crate::W<REG> {
53        self.variant(CHLEN::SixteenBit)
54    }
55    ///32-bit wide
56    #[inline(always)]
57    pub fn thirty_two_bit(self) -> &'a mut crate::W<REG> {
58        self.variant(CHLEN::ThirtyTwoBit)
59    }
60}
61/**Data length to be transferred
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum DATLEN {
68    ///0: 16-bit data length
69    SixteenBit = 0,
70    ///1: 24-bit data length
71    TwentyFourBit = 1,
72    ///2: 32-bit data length
73    ThirtyTwoBit = 2,
74}
75impl From<DATLEN> for u8 {
76    #[inline(always)]
77    fn from(variant: DATLEN) -> Self {
78        variant as _
79    }
80}
81impl crate::FieldSpec for DATLEN {
82    type Ux = u8;
83}
84impl crate::IsEnum for DATLEN {}
85///Field `DATLEN` reader - Data length to be transferred
86pub type DATLEN_R = crate::FieldReader<DATLEN>;
87impl DATLEN_R {
88    ///Get enumerated values variant
89    #[inline(always)]
90    pub const fn variant(&self) -> Option<DATLEN> {
91        match self.bits {
92            0 => Some(DATLEN::SixteenBit),
93            1 => Some(DATLEN::TwentyFourBit),
94            2 => Some(DATLEN::ThirtyTwoBit),
95            _ => None,
96        }
97    }
98    ///16-bit data length
99    #[inline(always)]
100    pub fn is_sixteen_bit(&self) -> bool {
101        *self == DATLEN::SixteenBit
102    }
103    ///24-bit data length
104    #[inline(always)]
105    pub fn is_twenty_four_bit(&self) -> bool {
106        *self == DATLEN::TwentyFourBit
107    }
108    ///32-bit data length
109    #[inline(always)]
110    pub fn is_thirty_two_bit(&self) -> bool {
111        *self == DATLEN::ThirtyTwoBit
112    }
113}
114///Field `DATLEN` writer - Data length to be transferred
115pub type DATLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATLEN>;
116impl<'a, REG> DATLEN_W<'a, REG>
117where
118    REG: crate::Writable + crate::RegisterSpec,
119    REG::Ux: From<u8>,
120{
121    ///16-bit data length
122    #[inline(always)]
123    pub fn sixteen_bit(self) -> &'a mut crate::W<REG> {
124        self.variant(DATLEN::SixteenBit)
125    }
126    ///24-bit data length
127    #[inline(always)]
128    pub fn twenty_four_bit(self) -> &'a mut crate::W<REG> {
129        self.variant(DATLEN::TwentyFourBit)
130    }
131    ///32-bit data length
132    #[inline(always)]
133    pub fn thirty_two_bit(self) -> &'a mut crate::W<REG> {
134        self.variant(DATLEN::ThirtyTwoBit)
135    }
136}
137/**Steady state clock polarity
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum CKPOL {
143    ///0: I2S clock inactive state is low level
144    IdleLow = 0,
145    ///1: I2S clock inactive state is high level
146    IdleHigh = 1,
147}
148impl From<CKPOL> for bool {
149    #[inline(always)]
150    fn from(variant: CKPOL) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `CKPOL` reader - Steady state clock polarity
155pub type CKPOL_R = crate::BitReader<CKPOL>;
156impl CKPOL_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> CKPOL {
160        match self.bits {
161            false => CKPOL::IdleLow,
162            true => CKPOL::IdleHigh,
163        }
164    }
165    ///I2S clock inactive state is low level
166    #[inline(always)]
167    pub fn is_idle_low(&self) -> bool {
168        *self == CKPOL::IdleLow
169    }
170    ///I2S clock inactive state is high level
171    #[inline(always)]
172    pub fn is_idle_high(&self) -> bool {
173        *self == CKPOL::IdleHigh
174    }
175}
176///Field `CKPOL` writer - Steady state clock polarity
177pub type CKPOL_W<'a, REG> = crate::BitWriter<'a, REG, CKPOL>;
178impl<'a, REG> CKPOL_W<'a, REG>
179where
180    REG: crate::Writable + crate::RegisterSpec,
181{
182    ///I2S clock inactive state is low level
183    #[inline(always)]
184    pub fn idle_low(self) -> &'a mut crate::W<REG> {
185        self.variant(CKPOL::IdleLow)
186    }
187    ///I2S clock inactive state is high level
188    #[inline(always)]
189    pub fn idle_high(self) -> &'a mut crate::W<REG> {
190        self.variant(CKPOL::IdleHigh)
191    }
192}
193/**I2S standard selection
194
195Value on reset: 0*/
196#[cfg_attr(feature = "defmt", derive(defmt::Format))]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198#[repr(u8)]
199pub enum I2SSTD {
200    ///0: I2S Philips standard
201    Philips = 0,
202    ///1: MSB justified standard
203    Msb = 1,
204    ///2: LSB justified standard
205    Lsb = 2,
206    ///3: PCM standard
207    Pcm = 3,
208}
209impl From<I2SSTD> for u8 {
210    #[inline(always)]
211    fn from(variant: I2SSTD) -> Self {
212        variant as _
213    }
214}
215impl crate::FieldSpec for I2SSTD {
216    type Ux = u8;
217}
218impl crate::IsEnum for I2SSTD {}
219///Field `I2SSTD` reader - I2S standard selection
220pub type I2SSTD_R = crate::FieldReader<I2SSTD>;
221impl I2SSTD_R {
222    ///Get enumerated values variant
223    #[inline(always)]
224    pub const fn variant(&self) -> I2SSTD {
225        match self.bits {
226            0 => I2SSTD::Philips,
227            1 => I2SSTD::Msb,
228            2 => I2SSTD::Lsb,
229            3 => I2SSTD::Pcm,
230            _ => unreachable!(),
231        }
232    }
233    ///I2S Philips standard
234    #[inline(always)]
235    pub fn is_philips(&self) -> bool {
236        *self == I2SSTD::Philips
237    }
238    ///MSB justified standard
239    #[inline(always)]
240    pub fn is_msb(&self) -> bool {
241        *self == I2SSTD::Msb
242    }
243    ///LSB justified standard
244    #[inline(always)]
245    pub fn is_lsb(&self) -> bool {
246        *self == I2SSTD::Lsb
247    }
248    ///PCM standard
249    #[inline(always)]
250    pub fn is_pcm(&self) -> bool {
251        *self == I2SSTD::Pcm
252    }
253}
254///Field `I2SSTD` writer - I2S standard selection
255pub type I2SSTD_W<'a, REG> = crate::FieldWriter<'a, REG, 2, I2SSTD, crate::Safe>;
256impl<'a, REG> I2SSTD_W<'a, REG>
257where
258    REG: crate::Writable + crate::RegisterSpec,
259    REG::Ux: From<u8>,
260{
261    ///I2S Philips standard
262    #[inline(always)]
263    pub fn philips(self) -> &'a mut crate::W<REG> {
264        self.variant(I2SSTD::Philips)
265    }
266    ///MSB justified standard
267    #[inline(always)]
268    pub fn msb(self) -> &'a mut crate::W<REG> {
269        self.variant(I2SSTD::Msb)
270    }
271    ///LSB justified standard
272    #[inline(always)]
273    pub fn lsb(self) -> &'a mut crate::W<REG> {
274        self.variant(I2SSTD::Lsb)
275    }
276    ///PCM standard
277    #[inline(always)]
278    pub fn pcm(self) -> &'a mut crate::W<REG> {
279        self.variant(I2SSTD::Pcm)
280    }
281}
282/**PCM frame synchronization
283
284Value on reset: 0*/
285#[cfg_attr(feature = "defmt", derive(defmt::Format))]
286#[derive(Clone, Copy, Debug, PartialEq, Eq)]
287pub enum PCMSYNC {
288    ///0: Short frame synchronisation
289    Short = 0,
290    ///1: Long frame synchronisation
291    Long = 1,
292}
293impl From<PCMSYNC> for bool {
294    #[inline(always)]
295    fn from(variant: PCMSYNC) -> Self {
296        variant as u8 != 0
297    }
298}
299///Field `PCMSYNC` reader - PCM frame synchronization
300pub type PCMSYNC_R = crate::BitReader<PCMSYNC>;
301impl PCMSYNC_R {
302    ///Get enumerated values variant
303    #[inline(always)]
304    pub const fn variant(&self) -> PCMSYNC {
305        match self.bits {
306            false => PCMSYNC::Short,
307            true => PCMSYNC::Long,
308        }
309    }
310    ///Short frame synchronisation
311    #[inline(always)]
312    pub fn is_short(&self) -> bool {
313        *self == PCMSYNC::Short
314    }
315    ///Long frame synchronisation
316    #[inline(always)]
317    pub fn is_long(&self) -> bool {
318        *self == PCMSYNC::Long
319    }
320}
321///Field `PCMSYNC` writer - PCM frame synchronization
322pub type PCMSYNC_W<'a, REG> = crate::BitWriter<'a, REG, PCMSYNC>;
323impl<'a, REG> PCMSYNC_W<'a, REG>
324where
325    REG: crate::Writable + crate::RegisterSpec,
326{
327    ///Short frame synchronisation
328    #[inline(always)]
329    pub fn short(self) -> &'a mut crate::W<REG> {
330        self.variant(PCMSYNC::Short)
331    }
332    ///Long frame synchronisation
333    #[inline(always)]
334    pub fn long(self) -> &'a mut crate::W<REG> {
335        self.variant(PCMSYNC::Long)
336    }
337}
338/**I2S configuration mode
339
340Value on reset: 0*/
341#[cfg_attr(feature = "defmt", derive(defmt::Format))]
342#[derive(Clone, Copy, Debug, PartialEq, Eq)]
343#[repr(u8)]
344pub enum I2SCFG {
345    ///0: Slave - transmit
346    SlaveTx = 0,
347    ///1: Slave - receive
348    SlaveRx = 1,
349    ///2: Master - transmit
350    MasterTx = 2,
351    ///3: Master - receive
352    MasterRx = 3,
353}
354impl From<I2SCFG> for u8 {
355    #[inline(always)]
356    fn from(variant: I2SCFG) -> Self {
357        variant as _
358    }
359}
360impl crate::FieldSpec for I2SCFG {
361    type Ux = u8;
362}
363impl crate::IsEnum for I2SCFG {}
364///Field `I2SCFG` reader - I2S configuration mode
365pub type I2SCFG_R = crate::FieldReader<I2SCFG>;
366impl I2SCFG_R {
367    ///Get enumerated values variant
368    #[inline(always)]
369    pub const fn variant(&self) -> I2SCFG {
370        match self.bits {
371            0 => I2SCFG::SlaveTx,
372            1 => I2SCFG::SlaveRx,
373            2 => I2SCFG::MasterTx,
374            3 => I2SCFG::MasterRx,
375            _ => unreachable!(),
376        }
377    }
378    ///Slave - transmit
379    #[inline(always)]
380    pub fn is_slave_tx(&self) -> bool {
381        *self == I2SCFG::SlaveTx
382    }
383    ///Slave - receive
384    #[inline(always)]
385    pub fn is_slave_rx(&self) -> bool {
386        *self == I2SCFG::SlaveRx
387    }
388    ///Master - transmit
389    #[inline(always)]
390    pub fn is_master_tx(&self) -> bool {
391        *self == I2SCFG::MasterTx
392    }
393    ///Master - receive
394    #[inline(always)]
395    pub fn is_master_rx(&self) -> bool {
396        *self == I2SCFG::MasterRx
397    }
398}
399///Field `I2SCFG` writer - I2S configuration mode
400pub type I2SCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, I2SCFG, crate::Safe>;
401impl<'a, REG> I2SCFG_W<'a, REG>
402where
403    REG: crate::Writable + crate::RegisterSpec,
404    REG::Ux: From<u8>,
405{
406    ///Slave - transmit
407    #[inline(always)]
408    pub fn slave_tx(self) -> &'a mut crate::W<REG> {
409        self.variant(I2SCFG::SlaveTx)
410    }
411    ///Slave - receive
412    #[inline(always)]
413    pub fn slave_rx(self) -> &'a mut crate::W<REG> {
414        self.variant(I2SCFG::SlaveRx)
415    }
416    ///Master - transmit
417    #[inline(always)]
418    pub fn master_tx(self) -> &'a mut crate::W<REG> {
419        self.variant(I2SCFG::MasterTx)
420    }
421    ///Master - receive
422    #[inline(always)]
423    pub fn master_rx(self) -> &'a mut crate::W<REG> {
424        self.variant(I2SCFG::MasterRx)
425    }
426}
427/**I2S Enable
428
429Value on reset: 0*/
430#[cfg_attr(feature = "defmt", derive(defmt::Format))]
431#[derive(Clone, Copy, Debug, PartialEq, Eq)]
432pub enum I2SE {
433    ///0: I2S peripheral is disabled
434    Disabled = 0,
435    ///1: I2S peripheral is enabled
436    Enabled = 1,
437}
438impl From<I2SE> for bool {
439    #[inline(always)]
440    fn from(variant: I2SE) -> Self {
441        variant as u8 != 0
442    }
443}
444///Field `I2SE` reader - I2S Enable
445pub type I2SE_R = crate::BitReader<I2SE>;
446impl I2SE_R {
447    ///Get enumerated values variant
448    #[inline(always)]
449    pub const fn variant(&self) -> I2SE {
450        match self.bits {
451            false => I2SE::Disabled,
452            true => I2SE::Enabled,
453        }
454    }
455    ///I2S peripheral is disabled
456    #[inline(always)]
457    pub fn is_disabled(&self) -> bool {
458        *self == I2SE::Disabled
459    }
460    ///I2S peripheral is enabled
461    #[inline(always)]
462    pub fn is_enabled(&self) -> bool {
463        *self == I2SE::Enabled
464    }
465}
466///Field `I2SE` writer - I2S Enable
467pub type I2SE_W<'a, REG> = crate::BitWriter<'a, REG, I2SE>;
468impl<'a, REG> I2SE_W<'a, REG>
469where
470    REG: crate::Writable + crate::RegisterSpec,
471{
472    ///I2S peripheral is disabled
473    #[inline(always)]
474    pub fn disabled(self) -> &'a mut crate::W<REG> {
475        self.variant(I2SE::Disabled)
476    }
477    ///I2S peripheral is enabled
478    #[inline(always)]
479    pub fn enabled(self) -> &'a mut crate::W<REG> {
480        self.variant(I2SE::Enabled)
481    }
482}
483/**I2S mode selection
484
485Value on reset: 0*/
486#[cfg_attr(feature = "defmt", derive(defmt::Format))]
487#[derive(Clone, Copy, Debug, PartialEq, Eq)]
488pub enum I2SMOD {
489    ///0: SPI mode is selected
490    Spimode = 0,
491    ///1: I2S mode is selected
492    I2smode = 1,
493}
494impl From<I2SMOD> for bool {
495    #[inline(always)]
496    fn from(variant: I2SMOD) -> Self {
497        variant as u8 != 0
498    }
499}
500///Field `I2SMOD` reader - I2S mode selection
501pub type I2SMOD_R = crate::BitReader<I2SMOD>;
502impl I2SMOD_R {
503    ///Get enumerated values variant
504    #[inline(always)]
505    pub const fn variant(&self) -> I2SMOD {
506        match self.bits {
507            false => I2SMOD::Spimode,
508            true => I2SMOD::I2smode,
509        }
510    }
511    ///SPI mode is selected
512    #[inline(always)]
513    pub fn is_spimode(&self) -> bool {
514        *self == I2SMOD::Spimode
515    }
516    ///I2S mode is selected
517    #[inline(always)]
518    pub fn is_i2smode(&self) -> bool {
519        *self == I2SMOD::I2smode
520    }
521}
522///Field `I2SMOD` writer - I2S mode selection
523pub type I2SMOD_W<'a, REG> = crate::BitWriter<'a, REG, I2SMOD>;
524impl<'a, REG> I2SMOD_W<'a, REG>
525where
526    REG: crate::Writable + crate::RegisterSpec,
527{
528    ///SPI mode is selected
529    #[inline(always)]
530    pub fn spimode(self) -> &'a mut crate::W<REG> {
531        self.variant(I2SMOD::Spimode)
532    }
533    ///I2S mode is selected
534    #[inline(always)]
535    pub fn i2smode(self) -> &'a mut crate::W<REG> {
536        self.variant(I2SMOD::I2smode)
537    }
538}
539impl R {
540    ///Bit 0 - Channel length (number of bits per audio channel)
541    #[inline(always)]
542    pub fn chlen(&self) -> CHLEN_R {
543        CHLEN_R::new((self.bits & 1) != 0)
544    }
545    ///Bits 1:2 - Data length to be transferred
546    #[inline(always)]
547    pub fn datlen(&self) -> DATLEN_R {
548        DATLEN_R::new(((self.bits >> 1) & 3) as u8)
549    }
550    ///Bit 3 - Steady state clock polarity
551    #[inline(always)]
552    pub fn ckpol(&self) -> CKPOL_R {
553        CKPOL_R::new(((self.bits >> 3) & 1) != 0)
554    }
555    ///Bits 4:5 - I2S standard selection
556    #[inline(always)]
557    pub fn i2sstd(&self) -> I2SSTD_R {
558        I2SSTD_R::new(((self.bits >> 4) & 3) as u8)
559    }
560    ///Bit 7 - PCM frame synchronization
561    #[inline(always)]
562    pub fn pcmsync(&self) -> PCMSYNC_R {
563        PCMSYNC_R::new(((self.bits >> 7) & 1) != 0)
564    }
565    ///Bits 8:9 - I2S configuration mode
566    #[inline(always)]
567    pub fn i2scfg(&self) -> I2SCFG_R {
568        I2SCFG_R::new(((self.bits >> 8) & 3) as u8)
569    }
570    ///Bit 10 - I2S Enable
571    #[inline(always)]
572    pub fn i2se(&self) -> I2SE_R {
573        I2SE_R::new(((self.bits >> 10) & 1) != 0)
574    }
575    ///Bit 11 - I2S mode selection
576    #[inline(always)]
577    pub fn i2smod(&self) -> I2SMOD_R {
578        I2SMOD_R::new(((self.bits >> 11) & 1) != 0)
579    }
580}
581impl core::fmt::Debug for R {
582    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
583        f.debug_struct("I2SCFGR")
584            .field("i2smod", &self.i2smod())
585            .field("i2se", &self.i2se())
586            .field("i2scfg", &self.i2scfg())
587            .field("pcmsync", &self.pcmsync())
588            .field("i2sstd", &self.i2sstd())
589            .field("ckpol", &self.ckpol())
590            .field("datlen", &self.datlen())
591            .field("chlen", &self.chlen())
592            .finish()
593    }
594}
595impl W {
596    ///Bit 0 - Channel length (number of bits per audio channel)
597    #[inline(always)]
598    pub fn chlen(&mut self) -> CHLEN_W<I2SCFGRrs> {
599        CHLEN_W::new(self, 0)
600    }
601    ///Bits 1:2 - Data length to be transferred
602    #[inline(always)]
603    pub fn datlen(&mut self) -> DATLEN_W<I2SCFGRrs> {
604        DATLEN_W::new(self, 1)
605    }
606    ///Bit 3 - Steady state clock polarity
607    #[inline(always)]
608    pub fn ckpol(&mut self) -> CKPOL_W<I2SCFGRrs> {
609        CKPOL_W::new(self, 3)
610    }
611    ///Bits 4:5 - I2S standard selection
612    #[inline(always)]
613    pub fn i2sstd(&mut self) -> I2SSTD_W<I2SCFGRrs> {
614        I2SSTD_W::new(self, 4)
615    }
616    ///Bit 7 - PCM frame synchronization
617    #[inline(always)]
618    pub fn pcmsync(&mut self) -> PCMSYNC_W<I2SCFGRrs> {
619        PCMSYNC_W::new(self, 7)
620    }
621    ///Bits 8:9 - I2S configuration mode
622    #[inline(always)]
623    pub fn i2scfg(&mut self) -> I2SCFG_W<I2SCFGRrs> {
624        I2SCFG_W::new(self, 8)
625    }
626    ///Bit 10 - I2S Enable
627    #[inline(always)]
628    pub fn i2se(&mut self) -> I2SE_W<I2SCFGRrs> {
629        I2SE_W::new(self, 10)
630    }
631    ///Bit 11 - I2S mode selection
632    #[inline(always)]
633    pub fn i2smod(&mut self) -> I2SMOD_W<I2SCFGRrs> {
634        I2SMOD_W::new(self, 11)
635    }
636}
637/**I2S configuration register
638
639You can [`read`](crate::Reg::read) this register and get [`i2scfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2scfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
640
641See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1:I2SCFGR)*/
642pub struct I2SCFGRrs;
643impl crate::RegisterSpec for I2SCFGRrs {
644    type Ux = u16;
645}
646///`read()` method returns [`i2scfgr::R`](R) reader structure
647impl crate::Readable for I2SCFGRrs {}
648///`write(|w| ..)` method takes [`i2scfgr::W`](W) writer structure
649impl crate::Writable for I2SCFGRrs {
650    type Safety = crate::Unsafe;
651}
652///`reset()` method sets I2SCFGR to value 0
653impl crate::Resettable for I2SCFGRrs {}
stm32f1_staging/stm32f107/spi1/i2scfgr.rs

stm32f1_staging/stm32f107/spi1/
i2scfgr.rs
