stm32f1_staging/stm32f107/
mod.rs

1/*!Peripheral access API for STM32F107 microcontrollers (generated using svd2rust v0.36.1 (a85deda 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{
16    CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU,
17};
18#[cfg(feature = "rt")]
19pub use cortex_m_rt::interrupt;
20#[cfg(feature = "rt")]
21extern "C" {
22    fn WWDG();
23    fn PVD();
24    fn TAMPER();
25    fn RTC();
26    fn FLASH();
27    fn RCC();
28    fn EXTI0();
29    fn EXTI1();
30    fn EXTI2();
31    fn EXTI3();
32    fn EXTI4();
33    fn DMA1_CHANNEL1();
34    fn DMA1_CHANNEL2();
35    fn DMA1_CHANNEL3();
36    fn DMA1_CHANNEL4();
37    fn DMA1_CHANNEL5();
38    fn DMA1_CHANNEL6();
39    fn DMA1_CHANNEL7();
40    fn ADC1_2();
41    fn USB_HP_CAN_TX();
42    fn USB_LP_CAN_RX0();
43    fn CAN_RX1();
44    fn CAN_SCE();
45    fn EXTI9_5();
46    fn TIM1_BRK();
47    fn TIM1_UP();
48    fn TIM1_TRG_COM();
49    fn TIM1_CC();
50    fn TIM2();
51    fn TIM3();
52    fn TIM4();
53    fn I2C1_EV();
54    fn I2C1_ER();
55    fn I2C2_EV();
56    fn I2C2_ER();
57    fn SPI1();
58    fn SPI2();
59    fn USART1();
60    fn USART2();
61    fn USART3();
62    fn EXTI15_10();
63    fn RTCALARM();
64    fn USBWAKEUP();
65    fn TIM8_BRK();
66    fn TIM8_UP();
67    fn TIM8_TRG_COM();
68    fn TIM8_CC();
69    fn ADC3();
70    fn FSMC();
71    fn SDIO();
72    fn TIM5();
73    fn SPI3();
74    fn UART4();
75    fn UART5();
76    fn TIM6();
77    fn TIM7();
78    fn DMA2_CHANNEL1();
79    fn DMA2_CHANNEL2();
80    fn DMA2_CHANNEL3();
81    fn DMA2_CHANNEL4();
82    fn DMA2_CHANNEL5();
83    fn ETH();
84    fn ETH_WKUP();
85    fn CAN2_TX();
86    fn CAN2_RX0();
87    fn CAN2_RX1();
88    fn CAN2_SCE();
89    fn OTG_FS();
90}
91#[doc(hidden)]
92#[repr(C)]
93pub union Vector {
94    _handler: unsafe extern "C" fn(),
95    _reserved: u32,
96}
97#[cfg(feature = "rt")]
98#[doc(hidden)]
99#[link_section = ".vector_table.interrupts"]
100#[no_mangle]
101pub static __INTERRUPTS: [Vector; 68] = [
102    Vector { _handler: WWDG },
103    Vector { _handler: PVD },
104    Vector { _handler: TAMPER },
105    Vector { _handler: RTC },
106    Vector { _handler: FLASH },
107    Vector { _handler: RCC },
108    Vector { _handler: EXTI0 },
109    Vector { _handler: EXTI1 },
110    Vector { _handler: EXTI2 },
111    Vector { _handler: EXTI3 },
112    Vector { _handler: EXTI4 },
113    Vector { _handler: DMA1_CHANNEL1 },
114    Vector { _handler: DMA1_CHANNEL2 },
115    Vector { _handler: DMA1_CHANNEL3 },
116    Vector { _handler: DMA1_CHANNEL4 },
117    Vector { _handler: DMA1_CHANNEL5 },
118    Vector { _handler: DMA1_CHANNEL6 },
119    Vector { _handler: DMA1_CHANNEL7 },
120    Vector { _handler: ADC1_2 },
121    Vector { _handler: USB_HP_CAN_TX },
122    Vector { _handler: USB_LP_CAN_RX0 },
123    Vector { _handler: CAN_RX1 },
124    Vector { _handler: CAN_SCE },
125    Vector { _handler: EXTI9_5 },
126    Vector { _handler: TIM1_BRK },
127    Vector { _handler: TIM1_UP },
128    Vector { _handler: TIM1_TRG_COM },
129    Vector { _handler: TIM1_CC },
130    Vector { _handler: TIM2 },
131    Vector { _handler: TIM3 },
132    Vector { _handler: TIM4 },
133    Vector { _handler: I2C1_EV },
134    Vector { _handler: I2C1_ER },
135    Vector { _handler: I2C2_EV },
136    Vector { _handler: I2C2_ER },
137    Vector { _handler: SPI1 },
138    Vector { _handler: SPI2 },
139    Vector { _handler: USART1 },
140    Vector { _handler: USART2 },
141    Vector { _handler: USART3 },
142    Vector { _handler: EXTI15_10 },
143    Vector { _handler: RTCALARM },
144    Vector { _handler: USBWAKEUP },
145    Vector { _handler: TIM8_BRK },
146    Vector { _handler: TIM8_UP },
147    Vector { _handler: TIM8_TRG_COM },
148    Vector { _handler: TIM8_CC },
149    Vector { _handler: ADC3 },
150    Vector { _handler: FSMC },
151    Vector { _handler: SDIO },
152    Vector { _handler: TIM5 },
153    Vector { _handler: SPI3 },
154    Vector { _handler: UART4 },
155    Vector { _handler: UART5 },
156    Vector { _handler: TIM6 },
157    Vector { _handler: TIM7 },
158    Vector { _handler: DMA2_CHANNEL1 },
159    Vector { _handler: DMA2_CHANNEL2 },
160    Vector { _handler: DMA2_CHANNEL3 },
161    Vector { _handler: DMA2_CHANNEL4 },
162    Vector { _handler: DMA2_CHANNEL5 },
163    Vector { _handler: ETH },
164    Vector { _handler: ETH_WKUP },
165    Vector { _handler: CAN2_TX },
166    Vector { _handler: CAN2_RX0 },
167    Vector { _handler: CAN2_RX1 },
168    Vector { _handler: CAN2_SCE },
169    Vector { _handler: OTG_FS },
170];
171///Enumeration of all the interrupts.
172#[cfg_attr(feature = "defmt", derive(defmt::Format))]
173#[derive(Copy, Clone, Debug, PartialEq, Eq)]
174#[repr(u16)]
175pub enum Interrupt {
176    ///0 - Window Watchdog interrupt
177    WWDG = 0,
178    ///1 - PVD through EXTI line detection interrupt
179    PVD = 1,
180    ///2 - Tamper interrupt
181    TAMPER = 2,
182    ///3 - RTC global interrupt
183    RTC = 3,
184    ///4 - Flash global interrupt
185    FLASH = 4,
186    ///5 - RCC global interrupt
187    RCC = 5,
188    ///6 - EXTI Line0 interrupt
189    EXTI0 = 6,
190    ///7 - EXTI Line1 interrupt
191    EXTI1 = 7,
192    ///8 - EXTI Line2 interrupt
193    EXTI2 = 8,
194    ///9 - EXTI Line3 interrupt
195    EXTI3 = 9,
196    ///10 - EXTI Line4 interrupt
197    EXTI4 = 10,
198    ///11 - DMA1 Channel1 global interrupt
199    DMA1_CHANNEL1 = 11,
200    ///12 - DMA1 Channel2 global interrupt
201    DMA1_CHANNEL2 = 12,
202    ///13 - DMA1 Channel3 global interrupt
203    DMA1_CHANNEL3 = 13,
204    ///14 - DMA1 Channel4 global interrupt
205    DMA1_CHANNEL4 = 14,
206    ///15 - DMA1 Channel5 global interrupt
207    DMA1_CHANNEL5 = 15,
208    ///16 - DMA1 Channel6 global interrupt
209    DMA1_CHANNEL6 = 16,
210    ///17 - DMA1 Channel7 global interrupt
211    DMA1_CHANNEL7 = 17,
212    ///18 - ADC1 and ADC2 global interrupt
213    ADC1_2 = 18,
214    ///19 - USB High Priority or CAN TX interrupts
215    USB_HP_CAN_TX = 19,
216    ///20 - USB Low Priority or CAN RX0 interrupts
217    USB_LP_CAN_RX0 = 20,
218    ///21 - CAN RX1 interrupts
219    CAN_RX1 = 21,
220    ///22 - CAN SCE interrupt
221    CAN_SCE = 22,
222    ///23 - EXTI Line\[9:5\] interrupts
223    EXTI9_5 = 23,
224    ///24 - TIM1 Break interrupt
225    TIM1_BRK = 24,
226    ///25 - TIM1 Update interrupt
227    TIM1_UP = 25,
228    ///26 - TIM1 Trigger and Commutation interrupts
229    TIM1_TRG_COM = 26,
230    ///27 - TIM1 Capture Compare interrupt
231    TIM1_CC = 27,
232    ///28 - TIM2 global interrupt
233    TIM2 = 28,
234    ///29 - TIM3 global interrupt
235    TIM3 = 29,
236    ///30 - TIM4 global interrupt
237    TIM4 = 30,
238    ///31 - I2C1 event interrupt
239    I2C1_EV = 31,
240    ///32 - I2C1 error interrupt
241    I2C1_ER = 32,
242    ///33 - I2C2 event interrupt
243    I2C2_EV = 33,
244    ///34 - I2C2 error interrupt
245    I2C2_ER = 34,
246    ///35 - SPI1 global interrupt
247    SPI1 = 35,
248    ///36 - SPI2 global interrupt
249    SPI2 = 36,
250    ///37 - USART1 global interrupt
251    USART1 = 37,
252    ///38 - USART2 global interrupt
253    USART2 = 38,
254    ///39 - USART3 global interrupt
255    USART3 = 39,
256    ///40 - EXTI Line\[15:10\] interrupts
257    EXTI15_10 = 40,
258    ///41 - RTC Alarms through EXTI line interrupt
259    RTCALARM = 41,
260    ///42 - USB wakeup from suspend through EXTI line interrupt
261    USBWAKEUP = 42,
262    ///43 - TIM8 Break interrupt
263    TIM8_BRK = 43,
264    ///44 - TIM8 Update interrupt
265    TIM8_UP = 44,
266    ///45 - TIM8 Trigger and Commutation interrupts
267    TIM8_TRG_COM = 45,
268    ///46 - TIM8 Capture Compare interrupt
269    TIM8_CC = 46,
270    ///47 - ADC3 global interrupt
271    ADC3 = 47,
272    ///48 - FSMC global interrupt
273    FSMC = 48,
274    ///49 - SDIO global interrupt
275    SDIO = 49,
276    ///50 - TIM5 global interrupt
277    TIM5 = 50,
278    ///51 - SPI3 global interrupt
279    SPI3 = 51,
280    ///52 - UART4 global interrupt
281    UART4 = 52,
282    ///53 - UART5 global interrupt
283    UART5 = 53,
284    ///54 - TIM6 global interrupt
285    TIM6 = 54,
286    ///55 - TIM7 global interrupt
287    TIM7 = 55,
288    ///56 - DMA2 Channel1 global interrupt
289    DMA2_CHANNEL1 = 56,
290    ///57 - DMA2 Channel2 global interrupt
291    DMA2_CHANNEL2 = 57,
292    ///58 - DMA2 Channel3 global interrupt
293    DMA2_CHANNEL3 = 58,
294    ///59 - DMA2 Channel4 global interrupt
295    DMA2_CHANNEL4 = 59,
296    ///60 - DMA2 Channel5 global interrupt
297    DMA2_CHANNEL5 = 60,
298    ///61 - Ethernet global interrupt
299    ETH = 61,
300    ///62 - Ethernet Wakeup through EXTI line interrupt
301    ETH_WKUP = 62,
302    ///63 - CAN2 TX interrupts
303    CAN2_TX = 63,
304    ///64 - CAN2 RX0 interrupts
305    CAN2_RX0 = 64,
306    ///65 - CAN2 RX1 interrupts
307    CAN2_RX1 = 65,
308    ///66 - CAN2 SCE interrupt
309    CAN2_SCE = 66,
310    ///67 - USB On The Go FS global interrupt
311    OTG_FS = 67,
312}
313unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
314    #[inline(always)]
315    fn number(self) -> u16 {
316        self as u16
317    }
318}
319///Power control
320///
321///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#PWR)
322pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
323impl core::fmt::Debug for PWR {
324    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
325        f.debug_struct("PWR").finish()
326    }
327}
328///Power control
329pub mod pwr;
330///Reset and clock control
331///
332///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC)
333pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
334impl core::fmt::Debug for RCC {
335    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
336        f.debug_struct("RCC").finish()
337    }
338}
339///Reset and clock control
340pub mod rcc;
341///General purpose I/O
342///
343///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
344pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
345impl core::fmt::Debug for GPIOA {
346    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
347        f.debug_struct("GPIOA").finish()
348    }
349}
350///General purpose I/O
351pub mod gpioa;
352///General purpose I/O
353///
354///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
355pub type GPIOB = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
356impl core::fmt::Debug for GPIOB {
357    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
358        f.debug_struct("GPIOB").finish()
359    }
360}
361///General purpose I/O
362pub use self::gpioa as gpiob;
363///General purpose I/O
364///
365///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
366pub type GPIOC = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
367impl core::fmt::Debug for GPIOC {
368    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
369        f.debug_struct("GPIOC").finish()
370    }
371}
372///General purpose I/O
373pub use self::gpioa as gpioc;
374///General purpose I/O
375///
376///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
377pub type GPIOD = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
378impl core::fmt::Debug for GPIOD {
379    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
380        f.debug_struct("GPIOD").finish()
381    }
382}
383///General purpose I/O
384pub use self::gpioa as gpiod;
385///General purpose I/O
386///
387///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
388pub type GPIOE = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
389impl core::fmt::Debug for GPIOE {
390    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
391        f.debug_struct("GPIOE").finish()
392    }
393}
394///General purpose I/O
395pub use self::gpioa as gpioe;
396///General purpose I/O
397///
398///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
399pub type GPIOF = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
400impl core::fmt::Debug for GPIOF {
401    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
402        f.debug_struct("GPIOF").finish()
403    }
404}
405///General purpose I/O
406pub use self::gpioa as gpiof;
407///General purpose I/O
408///
409///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
410pub type GPIOG = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
411impl core::fmt::Debug for GPIOG {
412    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
413        f.debug_struct("GPIOG").finish()
414    }
415}
416///General purpose I/O
417pub use self::gpioa as gpiog;
418///Alternate function I/O
419///
420///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#AFIO)
421pub type AFIO = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
422impl core::fmt::Debug for AFIO {
423    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
424        f.debug_struct("AFIO").finish()
425    }
426}
427///Alternate function I/O
428pub mod afio;
429///EXTI
430///
431///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#EXTI)
432pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
433impl core::fmt::Debug for EXTI {
434    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
435        f.debug_struct("EXTI").finish()
436    }
437}
438///EXTI
439pub mod exti;
440///DMA controller
441///
442///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DMA1)
443pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
444impl core::fmt::Debug for DMA1 {
445    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
446        f.debug_struct("DMA1").finish()
447    }
448}
449///DMA controller
450pub mod dma1;
451///DMA controller
452///
453///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DMA1)
454pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
455impl core::fmt::Debug for DMA2 {
456    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
457        f.debug_struct("DMA2").finish()
458    }
459}
460///DMA controller
461pub use self::dma1 as dma2;
462///Real time clock
463///
464///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RTC)
465pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
466impl core::fmt::Debug for RTC {
467    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
468        f.debug_struct("RTC").finish()
469    }
470}
471///Real time clock
472pub mod rtc;
473///Backup registers
474///
475///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#BKP)
476pub type BKP = crate::Periph<bkp::RegisterBlock, 0x4000_6c04>;
477impl core::fmt::Debug for BKP {
478    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
479        f.debug_struct("BKP").finish()
480    }
481}
482///Backup registers
483pub mod bkp;
484///Independent watchdog
485///
486///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#IWDG)
487pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
488impl core::fmt::Debug for IWDG {
489    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
490        f.debug_struct("IWDG").finish()
491    }
492}
493///Independent watchdog
494pub mod iwdg;
495///Window watchdog
496///
497///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#WWDG)
498pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
499impl core::fmt::Debug for WWDG {
500    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
501        f.debug_struct("WWDG").finish()
502    }
503}
504///Window watchdog
505pub mod wwdg;
506///Advanced timer
507///
508///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM1)
509pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
510impl core::fmt::Debug for TIM1 {
511    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
512        f.debug_struct("TIM1").finish()
513    }
514}
515///Advanced timer
516pub mod tim1;
517///General purpose timer
518///
519///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
520pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
521impl core::fmt::Debug for TIM2 {
522    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
523        f.debug_struct("TIM2").finish()
524    }
525}
526///General purpose timer
527pub mod tim2;
528///General purpose timer
529///
530///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
531pub type TIM3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
532impl core::fmt::Debug for TIM3 {
533    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
534        f.debug_struct("TIM3").finish()
535    }
536}
537///General purpose timer
538pub use self::tim2 as tim3;
539///General purpose timer
540///
541///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
542pub type TIM4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
543impl core::fmt::Debug for TIM4 {
544    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
545        f.debug_struct("TIM4").finish()
546    }
547}
548///General purpose timer
549pub use self::tim2 as tim4;
550///General purpose timer
551///
552///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
553pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
554impl core::fmt::Debug for TIM5 {
555    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
556        f.debug_struct("TIM5").finish()
557    }
558}
559///General purpose timer
560pub use self::tim2 as tim5;
561///Basic timer
562///
563///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM6)
564pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
565impl core::fmt::Debug for TIM6 {
566    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
567        f.debug_struct("TIM6").finish()
568    }
569}
570///Basic timer
571pub mod tim6;
572///Basic timer
573///
574///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM6)
575pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
576impl core::fmt::Debug for TIM7 {
577    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
578        f.debug_struct("TIM7").finish()
579    }
580}
581///Basic timer
582pub use self::tim6 as tim7;
583///Inter integrated circuit
584///
585///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#I2C1)
586pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
587impl core::fmt::Debug for I2C1 {
588    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
589        f.debug_struct("I2C1").finish()
590    }
591}
592///Inter integrated circuit
593pub mod i2c1;
594///Inter integrated circuit
595///
596///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#I2C1)
597pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
598impl core::fmt::Debug for I2C2 {
599    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
600        f.debug_struct("I2C2").finish()
601    }
602}
603///Inter integrated circuit
604pub use self::i2c1 as i2c2;
605///Serial peripheral interface
606///
607///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1)
608pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
609impl core::fmt::Debug for SPI1 {
610    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
611        f.debug_struct("SPI1").finish()
612    }
613}
614///Serial peripheral interface
615pub mod spi1;
616///Serial peripheral interface
617///
618///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1)
619pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
620impl core::fmt::Debug for SPI2 {
621    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
622        f.debug_struct("SPI2").finish()
623    }
624}
625///Serial peripheral interface
626pub use self::spi1 as spi2;
627///Serial peripheral interface
628///
629///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1)
630pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
631impl core::fmt::Debug for SPI3 {
632    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
633        f.debug_struct("SPI3").finish()
634    }
635}
636///Serial peripheral interface
637pub use self::spi1 as spi3;
638///Universal synchronous asynchronous receiver transmitter
639///
640///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1)
641pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
642impl core::fmt::Debug for USART1 {
643    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
644        f.debug_struct("USART1").finish()
645    }
646}
647///Universal synchronous asynchronous receiver transmitter
648pub mod usart1;
649///Universal synchronous asynchronous receiver transmitter
650///
651///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1)
652pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
653impl core::fmt::Debug for USART2 {
654    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
655        f.debug_struct("USART2").finish()
656    }
657}
658///Universal synchronous asynchronous receiver transmitter
659pub use self::usart1 as usart2;
660///Universal synchronous asynchronous receiver transmitter
661///
662///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1)
663pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
664impl core::fmt::Debug for USART3 {
665    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
666        f.debug_struct("USART3").finish()
667    }
668}
669///Universal synchronous asynchronous receiver transmitter
670pub use self::usart1 as usart3;
671///Analog to digital converter
672///
673///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC1)
674pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
675impl core::fmt::Debug for ADC1 {
676    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
677        f.debug_struct("ADC1").finish()
678    }
679}
680///Analog to digital converter
681pub mod adc1;
682///Analog to digital converter
683///
684///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC2)
685pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4001_2800>;
686impl core::fmt::Debug for ADC2 {
687    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
688        f.debug_struct("ADC2").finish()
689    }
690}
691///Analog to digital converter
692pub mod adc2;
693///Controller area network
694///
695///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#CAN1)
696pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
697impl core::fmt::Debug for CAN1 {
698    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
699        f.debug_struct("CAN1").finish()
700    }
701}
702///Controller area network
703pub mod can1;
704///Controller area network
705///
706///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#CAN1)
707pub type CAN2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
708impl core::fmt::Debug for CAN2 {
709    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
710        f.debug_struct("CAN2").finish()
711    }
712}
713///Controller area network
714pub use self::can1 as can2;
715///Ethernet: media access control
716///
717///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_MAC)
718pub type ETHERNET_MAC = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
719impl core::fmt::Debug for ETHERNET_MAC {
720    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
721        f.debug_struct("ETHERNET_MAC").finish()
722    }
723}
724///Ethernet: media access control
725pub mod ethernet_mac;
726///Ethernet: MAC management counters
727///
728///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_MMC)
729pub type ETHERNET_MMC = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
730impl core::fmt::Debug for ETHERNET_MMC {
731    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
732        f.debug_struct("ETHERNET_MMC").finish()
733    }
734}
735///Ethernet: MAC management counters
736pub mod ethernet_mmc;
737///Ethernet: Precision time protocol
738///
739///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_PTP)
740pub type ETHERNET_PTP = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
741impl core::fmt::Debug for ETHERNET_PTP {
742    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
743        f.debug_struct("ETHERNET_PTP").finish()
744    }
745}
746///Ethernet: Precision time protocol
747pub mod ethernet_ptp;
748///Ethernet: DMA controller operation
749///
750///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_DMA)
751pub type ETHERNET_DMA = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
752impl core::fmt::Debug for ETHERNET_DMA {
753    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
754        f.debug_struct("ETHERNET_DMA").finish()
755    }
756}
757///Ethernet: DMA controller operation
758pub mod ethernet_dma;
759///USB on the go full speed
760///
761///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_GLOBAL)
762pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
763impl core::fmt::Debug for OTG_FS_GLOBAL {
764    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
765        f.debug_struct("OTG_FS_GLOBAL").finish()
766    }
767}
768///USB on the go full speed
769pub mod otg_fs_global;
770///USB on the go full speed
771///
772///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_HOST)
773pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
774impl core::fmt::Debug for OTG_FS_HOST {
775    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
776        f.debug_struct("OTG_FS_HOST").finish()
777    }
778}
779///USB on the go full speed
780pub mod otg_fs_host;
781///USB on the go full speed
782///
783///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_DEVICE)
784pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
785impl core::fmt::Debug for OTG_FS_DEVICE {
786    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
787        f.debug_struct("OTG_FS_DEVICE").finish()
788    }
789}
790///USB on the go full speed
791pub mod otg_fs_device;
792///USB on the go full speed
793///
794///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_PWRCLK)
795pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
796impl core::fmt::Debug for OTG_FS_PWRCLK {
797    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
798        f.debug_struct("OTG_FS_PWRCLK").finish()
799    }
800}
801///USB on the go full speed
802pub mod otg_fs_pwrclk;
803///Digital to analog converter
804///
805///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DAC)
806pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
807impl core::fmt::Debug for DAC {
808    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
809        f.debug_struct("DAC").finish()
810    }
811}
812///Digital to analog converter
813pub mod dac;
814///Debug support
815///
816///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DBGMCU)
817pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
818impl core::fmt::Debug for DBGMCU {
819    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
820        f.debug_struct("DBGMCU").finish()
821    }
822}
823///Debug support
824pub mod dbgmcu;
825///Universal asynchronous receiver transmitter
826///
827///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4)
828pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
829impl core::fmt::Debug for UART4 {
830    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
831        f.debug_struct("UART4").finish()
832    }
833}
834///Universal asynchronous receiver transmitter
835pub mod uart4;
836///Universal asynchronous receiver transmitter
837///
838///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4)
839pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
840impl core::fmt::Debug for UART5 {
841    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
842        f.debug_struct("UART5").finish()
843    }
844}
845///Universal asynchronous receiver transmitter
846pub use self::uart4 as uart5;
847///CRC calculation unit
848///
849///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#CRC)
850pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
851impl core::fmt::Debug for CRC {
852    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
853        f.debug_struct("CRC").finish()
854    }
855}
856///CRC calculation unit
857pub mod crc;
858///FLASH
859///
860///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FLASH)
861pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
862impl core::fmt::Debug for FLASH {
863    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
864        f.debug_struct("FLASH").finish()
865    }
866}
867///FLASH
868pub mod flash;
869///Flexible static memory controller
870///
871///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC)
872pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
873impl core::fmt::Debug for FSMC {
874    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
875        f.debug_struct("FSMC").finish()
876    }
877}
878///Flexible static memory controller
879pub mod fsmc;
880///Secure digital input/output interface
881///
882///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO)
883pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_8000>;
884impl core::fmt::Debug for SDIO {
885    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
886        f.debug_struct("SDIO").finish()
887    }
888}
889///Secure digital input/output interface
890pub mod sdio;
891///General purpose timer
892///
893///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
894pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_1c00>;
895impl core::fmt::Debug for TIM13 {
896    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
897        f.debug_struct("TIM13").finish()
898    }
899}
900///General purpose timer
901pub mod tim13;
902///General purpose timer
903///
904///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
905pub type TIM11 = crate::Periph<tim13::RegisterBlock, 0x4001_5400>;
906impl core::fmt::Debug for TIM11 {
907    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
908        f.debug_struct("TIM11").finish()
909    }
910}
911///General purpose timer
912pub use self::tim13 as tim11;
913///General purpose timer
914///
915///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
916pub type TIM10 = crate::Periph<tim13::RegisterBlock, 0x4001_5000>;
917impl core::fmt::Debug for TIM10 {
918    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
919        f.debug_struct("TIM10").finish()
920    }
921}
922///General purpose timer
923pub use self::tim13 as tim10;
924///General purpose timer
925///
926///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM9)
927pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4c00>;
928impl core::fmt::Debug for TIM9 {
929    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
930        f.debug_struct("TIM9").finish()
931    }
932}
933///General purpose timer
934pub mod tim9;
935///General purpose timer
936///
937///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM9)
938pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
939impl core::fmt::Debug for TIM12 {
940    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
941        f.debug_struct("TIM12").finish()
942    }
943}
944///General purpose timer
945pub use self::tim9 as tim12;
946///Analog to digital converter
947///
948///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC3)
949pub type ADC3 = crate::Periph<adc3::RegisterBlock, 0x4001_3c00>;
950impl core::fmt::Debug for ADC3 {
951    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
952        f.debug_struct("ADC3").finish()
953    }
954}
955///Analog to digital converter
956pub mod adc3;
957///Advanced timer
958///
959///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM1)
960pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_3400>;
961impl core::fmt::Debug for TIM8 {
962    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
963        f.debug_struct("TIM8").finish()
964    }
965}
966///Advanced timer
967pub use self::tim1 as tim8;
968///Universal serial bus full-speed device interface
969///
970///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USB)
971pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
972impl core::fmt::Debug for USB {
973    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
974        f.debug_struct("USB").finish()
975    }
976}
977///Universal serial bus full-speed device interface
978pub mod usb;
979///General purpose timer
980///
981///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
982pub type TIM14 = crate::Periph<tim13::RegisterBlock, 0x4000_2000>;
983impl core::fmt::Debug for TIM14 {
984    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
985        f.debug_struct("TIM14").finish()
986    }
987}
988///General purpose timer
989pub use self::tim13 as tim14;
990///System control block ACTLR
991///
992///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SCB_ACTRL)
993pub type SCB_ACTRL = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
994impl core::fmt::Debug for SCB_ACTRL {
995    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
996        f.debug_struct("SCB_ACTRL").finish()
997    }
998}
999///System control block ACTLR
1000pub mod scb_actrl;
1001///Nested vectored interrupt controller
1002///
1003///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#NVIC_STIR)
1004pub type NVIC_STIR = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
1005impl core::fmt::Debug for NVIC_STIR {
1006    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1007        f.debug_struct("NVIC_STIR").finish()
1008    }
1009}
1010///Nested vectored interrupt controller
1011pub mod nvic_stir;
1012///SysTick timer
1013///
1014///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#STK)
1015pub type STK = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
1016impl core::fmt::Debug for STK {
1017    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1018        f.debug_struct("STK").finish()
1019    }
1020}
1021///SysTick timer
1022pub mod stk;
1023#[no_mangle]
1024static mut DEVICE_PERIPHERALS: bool = false;
1025/// All the peripherals.
1026#[allow(non_snake_case)]
1027pub struct Peripherals {
1028    ///PWR
1029    pub PWR: PWR,
1030    ///RCC
1031    pub RCC: RCC,
1032    ///GPIOA
1033    pub GPIOA: GPIOA,
1034    ///GPIOB
1035    pub GPIOB: GPIOB,
1036    ///GPIOC
1037    pub GPIOC: GPIOC,
1038    ///GPIOD
1039    pub GPIOD: GPIOD,
1040    ///GPIOE
1041    pub GPIOE: GPIOE,
1042    ///GPIOF
1043    pub GPIOF: GPIOF,
1044    ///GPIOG
1045    pub GPIOG: GPIOG,
1046    ///AFIO
1047    pub AFIO: AFIO,
1048    ///EXTI
1049    pub EXTI: EXTI,
1050    ///DMA1
1051    pub DMA1: DMA1,
1052    ///DMA2
1053    pub DMA2: DMA2,
1054    ///RTC
1055    pub RTC: RTC,
1056    ///BKP
1057    pub BKP: BKP,
1058    ///IWDG
1059    pub IWDG: IWDG,
1060    ///WWDG
1061    pub WWDG: WWDG,
1062    ///TIM1
1063    pub TIM1: TIM1,
1064    ///TIM2
1065    pub TIM2: TIM2,
1066    ///TIM3
1067    pub TIM3: TIM3,
1068    ///TIM4
1069    pub TIM4: TIM4,
1070    ///TIM5
1071    pub TIM5: TIM5,
1072    ///TIM6
1073    pub TIM6: TIM6,
1074    ///TIM7
1075    pub TIM7: TIM7,
1076    ///I2C1
1077    pub I2C1: I2C1,
1078    ///I2C2
1079    pub I2C2: I2C2,
1080    ///SPI1
1081    pub SPI1: SPI1,
1082    ///SPI2
1083    pub SPI2: SPI2,
1084    ///SPI3
1085    pub SPI3: SPI3,
1086    ///USART1
1087    pub USART1: USART1,
1088    ///USART2
1089    pub USART2: USART2,
1090    ///USART3
1091    pub USART3: USART3,
1092    ///ADC1
1093    pub ADC1: ADC1,
1094    ///ADC2
1095    pub ADC2: ADC2,
1096    ///CAN1
1097    pub CAN1: CAN1,
1098    ///CAN2
1099    pub CAN2: CAN2,
1100    ///Ethernet_MAC
1101    pub ETHERNET_MAC: ETHERNET_MAC,
1102    ///Ethernet_MMC
1103    pub ETHERNET_MMC: ETHERNET_MMC,
1104    ///Ethernet_PTP
1105    pub ETHERNET_PTP: ETHERNET_PTP,
1106    ///Ethernet_DMA
1107    pub ETHERNET_DMA: ETHERNET_DMA,
1108    ///OTG_FS_GLOBAL
1109    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1110    ///OTG_FS_HOST
1111    pub OTG_FS_HOST: OTG_FS_HOST,
1112    ///OTG_FS_DEVICE
1113    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1114    ///OTG_FS_PWRCLK
1115    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1116    ///DAC
1117    pub DAC: DAC,
1118    ///DBGMCU
1119    pub DBGMCU: DBGMCU,
1120    ///UART4
1121    pub UART4: UART4,
1122    ///UART5
1123    pub UART5: UART5,
1124    ///CRC
1125    pub CRC: CRC,
1126    ///FLASH
1127    pub FLASH: FLASH,
1128    ///FSMC
1129    pub FSMC: FSMC,
1130    ///SDIO
1131    pub SDIO: SDIO,
1132    ///TIM13
1133    pub TIM13: TIM13,
1134    ///TIM11
1135    pub TIM11: TIM11,
1136    ///TIM10
1137    pub TIM10: TIM10,
1138    ///TIM9
1139    pub TIM9: TIM9,
1140    ///TIM12
1141    pub TIM12: TIM12,
1142    ///ADC3
1143    pub ADC3: ADC3,
1144    ///TIM8
1145    pub TIM8: TIM8,
1146    ///USB
1147    pub USB: USB,
1148    ///TIM14
1149    pub TIM14: TIM14,
1150    ///SCB_ACTRL
1151    pub SCB_ACTRL: SCB_ACTRL,
1152    ///NVIC_STIR
1153    pub NVIC_STIR: NVIC_STIR,
1154    ///STK
1155    pub STK: STK,
1156}
1157impl Peripherals {
1158    /// Returns all the peripherals *once*.
1159    #[cfg(feature = "critical-section")]
1160    #[inline]
1161    pub fn take() -> Option<Self> {
1162        critical_section::with(|_| {
1163            if unsafe { DEVICE_PERIPHERALS } {
1164                return None;
1165            }
1166            Some(unsafe { Peripherals::steal() })
1167        })
1168    }
1169    /// Unchecked version of `Peripherals::take`.
1170    ///
1171    /// # Safety
1172    ///
1173    /// Each of the returned peripherals must be used at most once.
1174    #[inline]
1175    pub unsafe fn steal() -> Self {
1176        DEVICE_PERIPHERALS = true;
1177        Peripherals {
1178            PWR: PWR::steal(),
1179            RCC: RCC::steal(),
1180            GPIOA: GPIOA::steal(),
1181            GPIOB: GPIOB::steal(),
1182            GPIOC: GPIOC::steal(),
1183            GPIOD: GPIOD::steal(),
1184            GPIOE: GPIOE::steal(),
1185            GPIOF: GPIOF::steal(),
1186            GPIOG: GPIOG::steal(),
1187            AFIO: AFIO::steal(),
1188            EXTI: EXTI::steal(),
1189            DMA1: DMA1::steal(),
1190            DMA2: DMA2::steal(),
1191            RTC: RTC::steal(),
1192            BKP: BKP::steal(),
1193            IWDG: IWDG::steal(),
1194            WWDG: WWDG::steal(),
1195            TIM1: TIM1::steal(),
1196            TIM2: TIM2::steal(),
1197            TIM3: TIM3::steal(),
1198            TIM4: TIM4::steal(),
1199            TIM5: TIM5::steal(),
1200            TIM6: TIM6::steal(),
1201            TIM7: TIM7::steal(),
1202            I2C1: I2C1::steal(),
1203            I2C2: I2C2::steal(),
1204            SPI1: SPI1::steal(),
1205            SPI2: SPI2::steal(),
1206            SPI3: SPI3::steal(),
1207            USART1: USART1::steal(),
1208            USART2: USART2::steal(),
1209            USART3: USART3::steal(),
1210            ADC1: ADC1::steal(),
1211            ADC2: ADC2::steal(),
1212            CAN1: CAN1::steal(),
1213            CAN2: CAN2::steal(),
1214            ETHERNET_MAC: ETHERNET_MAC::steal(),
1215            ETHERNET_MMC: ETHERNET_MMC::steal(),
1216            ETHERNET_PTP: ETHERNET_PTP::steal(),
1217            ETHERNET_DMA: ETHERNET_DMA::steal(),
1218            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1219            OTG_FS_HOST: OTG_FS_HOST::steal(),
1220            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1221            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1222            DAC: DAC::steal(),
1223            DBGMCU: DBGMCU::steal(),
1224            UART4: UART4::steal(),
1225            UART5: UART5::steal(),
1226            CRC: CRC::steal(),
1227            FLASH: FLASH::steal(),
1228            FSMC: FSMC::steal(),
1229            SDIO: SDIO::steal(),
1230            TIM13: TIM13::steal(),
1231            TIM11: TIM11::steal(),
1232            TIM10: TIM10::steal(),
1233            TIM9: TIM9::steal(),
1234            TIM12: TIM12::steal(),
1235            ADC3: ADC3::steal(),
1236            TIM8: TIM8::steal(),
1237            USB: USB::steal(),
1238            TIM14: TIM14::steal(),
1239            SCB_ACTRL: SCB_ACTRL::steal(),
1240            NVIC_STIR: NVIC_STIR::steal(),
1241            STK: STK::steal(),
1242        }
1243    }
1244}
stm32f1_staging/stm32f107/mod.rs

stm32f1_staging/stm32f107/
mod.rs
