stm32f1_staging/stm32f107/gpioa/
idr.rs

1///Register `IDR` reader
2pub type R = crate::R<IDRrs>;
3/**Port input data
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum INPUT_DATA {
9    ///0: Input is logic low
10    Low = 0,
11    ///1: Input is logic high
12    High = 1,
13}
14impl From<INPUT_DATA> for bool {
15    #[inline(always)]
16    fn from(variant: INPUT_DATA) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `IDR(0-15)` reader - Port input data
21pub type IDR_R = crate::BitReader<INPUT_DATA>;
22impl IDR_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> INPUT_DATA {
26        match self.bits {
27            false => INPUT_DATA::Low,
28            true => INPUT_DATA::High,
29        }
30    }
31    ///Input is logic low
32    #[inline(always)]
33    pub fn is_low(&self) -> bool {
34        *self == INPUT_DATA::Low
35    }
36    ///Input is logic high
37    #[inline(always)]
38    pub fn is_high(&self) -> bool {
39        *self == INPUT_DATA::High
40    }
41}
42impl R {
43    ///Port input data
44    ///
45    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IDR0` field.</div>
46    #[inline(always)]
47    pub fn idr(&self, n: u8) -> IDR_R {
48        #[allow(clippy::no_effect)] [(); 16][n as usize];
49        IDR_R::new(((self.bits >> n) & 1) != 0)
50    }
51    ///Iterator for array of:
52    ///Port input data
53    #[inline(always)]
54    pub fn idr_iter(&self) -> impl Iterator<Item = IDR_R> + '_ {
55        (0..16).map(move |n| IDR_R::new(((self.bits >> n) & 1) != 0))
56    }
57    ///Bit 0 - Port input data
58    #[inline(always)]
59    pub fn idr0(&self) -> IDR_R {
60        IDR_R::new((self.bits & 1) != 0)
61    }
62    ///Bit 1 - Port input data
63    #[inline(always)]
64    pub fn idr1(&self) -> IDR_R {
65        IDR_R::new(((self.bits >> 1) & 1) != 0)
66    }
67    ///Bit 2 - Port input data
68    #[inline(always)]
69    pub fn idr2(&self) -> IDR_R {
70        IDR_R::new(((self.bits >> 2) & 1) != 0)
71    }
72    ///Bit 3 - Port input data
73    #[inline(always)]
74    pub fn idr3(&self) -> IDR_R {
75        IDR_R::new(((self.bits >> 3) & 1) != 0)
76    }
77    ///Bit 4 - Port input data
78    #[inline(always)]
79    pub fn idr4(&self) -> IDR_R {
80        IDR_R::new(((self.bits >> 4) & 1) != 0)
81    }
82    ///Bit 5 - Port input data
83    #[inline(always)]
84    pub fn idr5(&self) -> IDR_R {
85        IDR_R::new(((self.bits >> 5) & 1) != 0)
86    }
87    ///Bit 6 - Port input data
88    #[inline(always)]
89    pub fn idr6(&self) -> IDR_R {
90        IDR_R::new(((self.bits >> 6) & 1) != 0)
91    }
92    ///Bit 7 - Port input data
93    #[inline(always)]
94    pub fn idr7(&self) -> IDR_R {
95        IDR_R::new(((self.bits >> 7) & 1) != 0)
96    }
97    ///Bit 8 - Port input data
98    #[inline(always)]
99    pub fn idr8(&self) -> IDR_R {
100        IDR_R::new(((self.bits >> 8) & 1) != 0)
101    }
102    ///Bit 9 - Port input data
103    #[inline(always)]
104    pub fn idr9(&self) -> IDR_R {
105        IDR_R::new(((self.bits >> 9) & 1) != 0)
106    }
107    ///Bit 10 - Port input data
108    #[inline(always)]
109    pub fn idr10(&self) -> IDR_R {
110        IDR_R::new(((self.bits >> 10) & 1) != 0)
111    }
112    ///Bit 11 - Port input data
113    #[inline(always)]
114    pub fn idr11(&self) -> IDR_R {
115        IDR_R::new(((self.bits >> 11) & 1) != 0)
116    }
117    ///Bit 12 - Port input data
118    #[inline(always)]
119    pub fn idr12(&self) -> IDR_R {
120        IDR_R::new(((self.bits >> 12) & 1) != 0)
121    }
122    ///Bit 13 - Port input data
123    #[inline(always)]
124    pub fn idr13(&self) -> IDR_R {
125        IDR_R::new(((self.bits >> 13) & 1) != 0)
126    }
127    ///Bit 14 - Port input data
128    #[inline(always)]
129    pub fn idr14(&self) -> IDR_R {
130        IDR_R::new(((self.bits >> 14) & 1) != 0)
131    }
132    ///Bit 15 - Port input data
133    #[inline(always)]
134    pub fn idr15(&self) -> IDR_R {
135        IDR_R::new(((self.bits >> 15) & 1) != 0)
136    }
137}
138impl core::fmt::Debug for R {
139    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
140        f.debug_struct("IDR")
141            .field("idr0", &self.idr0())
142            .field("idr1", &self.idr1())
143            .field("idr2", &self.idr2())
144            .field("idr3", &self.idr3())
145            .field("idr4", &self.idr4())
146            .field("idr5", &self.idr5())
147            .field("idr6", &self.idr6())
148            .field("idr7", &self.idr7())
149            .field("idr8", &self.idr8())
150            .field("idr9", &self.idr9())
151            .field("idr10", &self.idr10())
152            .field("idr11", &self.idr11())
153            .field("idr12", &self.idr12())
154            .field("idr13", &self.idr13())
155            .field("idr14", &self.idr14())
156            .field("idr15", &self.idr15())
157            .finish()
158    }
159}
160/**Port input data register (GPIOn_IDR)
161
162You can [`read`](crate::Reg::read) this register and get [`idr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
163
164See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA:IDR)*/
165pub struct IDRrs;
166impl crate::RegisterSpec for IDRrs {
167    type Ux = u32;
168}
169///`read()` method returns [`idr::R`](R) reader structure
170impl crate::Readable for IDRrs {}
171///`reset()` method sets IDR to value 0
172impl crate::Resettable for IDRrs {}
stm32f1_staging/stm32f107/gpioa/idr.rs

stm32f1_staging/stm32f107/gpioa/
idr.rs
