stm32f1_staging/stm32f107/gpioa/
brr.rs

1///Register `BRR` writer
2pub type W = crate::W<BRRrs>;
3/**Reset bit %s
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum BIT_RESET {
9    ///0: No action on the corresponding ODx bit
10    NoAction = 0,
11    ///1: Reset the ODx bit
12    Reset = 1,
13}
14impl From<BIT_RESET> for bool {
15    #[inline(always)]
16    fn from(variant: BIT_RESET) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `BR(0-15)` writer - Reset bit %s
21pub type BR_W<'a, REG> = crate::BitWriter<'a, REG, BIT_RESET>;
22impl<'a, REG> BR_W<'a, REG>
23where
24    REG: crate::Writable + crate::RegisterSpec,
25{
26    ///No action on the corresponding ODx bit
27    #[inline(always)]
28    pub fn no_action(self) -> &'a mut crate::W<REG> {
29        self.variant(BIT_RESET::NoAction)
30    }
31    ///Reset the ODx bit
32    #[inline(always)]
33    pub fn reset(self) -> &'a mut crate::W<REG> {
34        self.variant(BIT_RESET::Reset)
35    }
36}
37impl core::fmt::Debug for crate::generic::Reg<BRRrs> {
38    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
39        write!(f, "(not readable)")
40    }
41}
42impl W {
43    ///Reset bit (0-15)
44    ///
45    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BR0` field.</div>
46    #[inline(always)]
47    pub fn br(&mut self, n: u8) -> BR_W<BRRrs> {
48        #[allow(clippy::no_effect)] [(); 16][n as usize];
49        BR_W::new(self, n)
50    }
51    ///Bit 0 - Reset bit 0
52    #[inline(always)]
53    pub fn br0(&mut self) -> BR_W<BRRrs> {
54        BR_W::new(self, 0)
55    }
56    ///Bit 1 - Reset bit 1
57    #[inline(always)]
58    pub fn br1(&mut self) -> BR_W<BRRrs> {
59        BR_W::new(self, 1)
60    }
61    ///Bit 2 - Reset bit 2
62    #[inline(always)]
63    pub fn br2(&mut self) -> BR_W<BRRrs> {
64        BR_W::new(self, 2)
65    }
66    ///Bit 3 - Reset bit 3
67    #[inline(always)]
68    pub fn br3(&mut self) -> BR_W<BRRrs> {
69        BR_W::new(self, 3)
70    }
71    ///Bit 4 - Reset bit 4
72    #[inline(always)]
73    pub fn br4(&mut self) -> BR_W<BRRrs> {
74        BR_W::new(self, 4)
75    }
76    ///Bit 5 - Reset bit 5
77    #[inline(always)]
78    pub fn br5(&mut self) -> BR_W<BRRrs> {
79        BR_W::new(self, 5)
80    }
81    ///Bit 6 - Reset bit 6
82    #[inline(always)]
83    pub fn br6(&mut self) -> BR_W<BRRrs> {
84        BR_W::new(self, 6)
85    }
86    ///Bit 7 - Reset bit 7
87    #[inline(always)]
88    pub fn br7(&mut self) -> BR_W<BRRrs> {
89        BR_W::new(self, 7)
90    }
91    ///Bit 8 - Reset bit 8
92    #[inline(always)]
93    pub fn br8(&mut self) -> BR_W<BRRrs> {
94        BR_W::new(self, 8)
95    }
96    ///Bit 9 - Reset bit 9
97    #[inline(always)]
98    pub fn br9(&mut self) -> BR_W<BRRrs> {
99        BR_W::new(self, 9)
100    }
101    ///Bit 10 - Reset bit 10
102    #[inline(always)]
103    pub fn br10(&mut self) -> BR_W<BRRrs> {
104        BR_W::new(self, 10)
105    }
106    ///Bit 11 - Reset bit 11
107    #[inline(always)]
108    pub fn br11(&mut self) -> BR_W<BRRrs> {
109        BR_W::new(self, 11)
110    }
111    ///Bit 12 - Reset bit 12
112    #[inline(always)]
113    pub fn br12(&mut self) -> BR_W<BRRrs> {
114        BR_W::new(self, 12)
115    }
116    ///Bit 13 - Reset bit 13
117    #[inline(always)]
118    pub fn br13(&mut self) -> BR_W<BRRrs> {
119        BR_W::new(self, 13)
120    }
121    ///Bit 14 - Reset bit 14
122    #[inline(always)]
123    pub fn br14(&mut self) -> BR_W<BRRrs> {
124        BR_W::new(self, 14)
125    }
126    ///Bit 15 - Reset bit 15
127    #[inline(always)]
128    pub fn br15(&mut self) -> BR_W<BRRrs> {
129        BR_W::new(self, 15)
130    }
131}
132/**Port bit reset register (GPIOn_BRR)
133
134You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
135
136See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA:BRR)*/
137pub struct BRRrs;
138impl crate::RegisterSpec for BRRrs {
139    type Ux = u32;
140}
141///`write(|w| ..)` method takes [`brr::W`](W) writer structure
142impl crate::Writable for BRRrs {
143    type Safety = crate::Unsafe;
144}
145///`reset()` method sets BRR to value 0
146impl crate::Resettable for BRRrs {}
stm32f1_staging/stm32f107/gpioa/brr.rs

stm32f1_staging/stm32f107/gpioa/
brr.rs
