stm32f1_staging/stm32f103/tim6/
egr.rs

1///Register `EGR` writer
2pub type W = crate::W<EGRrs>;
3/**Update generation
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum UG {
9    ///1: Re-initializes the timer counter and generates an update of the registers.
10    Update = 1,
11}
12impl From<UG> for bool {
13    #[inline(always)]
14    fn from(variant: UG) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `UG` writer - Update generation
19pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
20impl<'a, REG> UG_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Re-initializes the timer counter and generates an update of the registers.
25    #[inline(always)]
26    pub fn update(self) -> &'a mut crate::W<REG> {
27        self.variant(UG::Update)
28    }
29}
30impl core::fmt::Debug for crate::generic::Reg<EGRrs> {
31    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
32        write!(f, "(not readable)")
33    }
34}
35impl W {
36    ///Bit 0 - Update generation
37    #[inline(always)]
38    pub fn ug(&mut self) -> UG_W<EGRrs> {
39        UG_W::new(self, 0)
40    }
41}
42/**event generation register
43
44You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
45
46See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM6:EGR)*/
47pub struct EGRrs;
48impl crate::RegisterSpec for EGRrs {
49    type Ux = u32;
50}
51///`write(|w| ..)` method takes [`egr::W`](W) writer structure
52impl crate::Writable for EGRrs {
53    type Safety = crate::Unsafe;
54}
55///`reset()` method sets EGR to value 0
56impl crate::Resettable for EGRrs {}
stm32f1_staging/stm32f103/tim6/egr.rs

stm32f1_staging/stm32f103/tim6/
egr.rs
