stm32f1_staging/stm32f103/tim10/
egr.rs

1///Register `EGR` writer
2pub type W = crate::W<EGRrs>;
3/**Update generation
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum UG {
9    ///1: Re-initializes the timer counter and generates an update of the registers.
10    Update = 1,
11}
12impl From<UG> for bool {
13    #[inline(always)]
14    fn from(variant: UG) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `UG` writer - Update generation
19pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
20impl<'a, REG> UG_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Re-initializes the timer counter and generates an update of the registers.
25    #[inline(always)]
26    pub fn update(self) -> &'a mut crate::W<REG> {
27        self.variant(UG::Update)
28    }
29}
30/**Capture/compare %s generation
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum CC1GW {
36    ///1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
37    Trigger = 1,
38}
39impl From<CC1GW> for bool {
40    #[inline(always)]
41    fn from(variant: CC1GW) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `CCG(1-1)` writer - Capture/compare %s generation
46pub type CCG_W<'a, REG> = crate::BitWriter<'a, REG, CC1GW>;
47impl<'a, REG> CCG_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
52    #[inline(always)]
53    pub fn trigger(self) -> &'a mut crate::W<REG> {
54        self.variant(CC1GW::Trigger)
55    }
56}
57impl core::fmt::Debug for crate::generic::Reg<EGRrs> {
58    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
59        write!(f, "(not readable)")
60    }
61}
62impl W {
63    ///Bit 0 - Update generation
64    #[inline(always)]
65    pub fn ug(&mut self) -> UG_W<EGRrs> {
66        UG_W::new(self, 0)
67    }
68    ///Capture/compare (1-1) generation
69    ///
70    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1G` field.</div>
71    #[inline(always)]
72    pub fn ccg(&mut self, n: u8) -> CCG_W<EGRrs> {
73        #[allow(clippy::no_effect)] [(); 1][n as usize];
74        CCG_W::new(self, n * 0 + 1)
75    }
76    ///Bit 1 - Capture/compare 1 generation
77    #[inline(always)]
78    pub fn cc1g(&mut self) -> CCG_W<EGRrs> {
79        CCG_W::new(self, 1)
80    }
81}
82/**event generation register
83
84You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
85
86See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM10:EGR)*/
87pub struct EGRrs;
88impl crate::RegisterSpec for EGRrs {
89    type Ux = u32;
90}
91///`write(|w| ..)` method takes [`egr::W`](W) writer structure
92impl crate::Writable for EGRrs {
93    type Safety = crate::Unsafe;
94}
95///`reset()` method sets EGR to value 0
96impl crate::Resettable for EGRrs {}
stm32f1_staging/stm32f103/tim10/egr.rs

stm32f1_staging/stm32f103/tim10/
egr.rs
