stm32f1_staging/stm32f103/
rcc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    cfgr: CFGR,
7    cir: CIR,
8    apb2rstr: APB2RSTR,
9    apb1rstr: APB1RSTR,
10    ahbenr: AHBENR,
11    apb2enr: APB2ENR,
12    apb1enr: APB1ENR,
13    bdcr: BDCR,
14    csr: CSR,
15}
16impl RegisterBlock {
17    ///0x00 - Clock control register
18    #[inline(always)]
19    pub const fn cr(&self) -> &CR {
20        &self.cr
21    }
22    ///0x04 - Clock configuration register (RCC_CFGR)
23    #[inline(always)]
24    pub const fn cfgr(&self) -> &CFGR {
25        &self.cfgr
26    }
27    ///0x08 - Clock interrupt register (RCC_CIR)
28    #[inline(always)]
29    pub const fn cir(&self) -> &CIR {
30        &self.cir
31    }
32    ///0x0c - APB2 peripheral reset register (RCC_APB2RSTR)
33    #[inline(always)]
34    pub const fn apb2rstr(&self) -> &APB2RSTR {
35        &self.apb2rstr
36    }
37    ///0x10 - APB1 peripheral reset register (RCC_APB1RSTR)
38    #[inline(always)]
39    pub const fn apb1rstr(&self) -> &APB1RSTR {
40        &self.apb1rstr
41    }
42    ///0x14 - AHB Peripheral Clock enable register (RCC_AHBENR)
43    #[inline(always)]
44    pub const fn ahbenr(&self) -> &AHBENR {
45        &self.ahbenr
46    }
47    ///0x18 - APB2 peripheral clock enable register (RCC_APB2ENR)
48    #[inline(always)]
49    pub const fn apb2enr(&self) -> &APB2ENR {
50        &self.apb2enr
51    }
52    ///0x1c - APB1 peripheral clock enable register (RCC_APB1ENR)
53    #[inline(always)]
54    pub const fn apb1enr(&self) -> &APB1ENR {
55        &self.apb1enr
56    }
57    ///0x20 - Backup domain control register (RCC_BDCR)
58    #[inline(always)]
59    pub const fn bdcr(&self) -> &BDCR {
60        &self.bdcr
61    }
62    ///0x24 - Control/status register (RCC_CSR)
63    #[inline(always)]
64    pub const fn csr(&self) -> &CSR {
65        &self.csr
66    }
67}
68/**CR (rw) register accessor: Clock control register
69
70You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
71
72See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:CR)
73
74For information about available fields see [`mod@cr`] module*/
75pub type CR = crate::Reg<cr::CRrs>;
76///Clock control register
77pub mod cr;
78/**CFGR (rw) register accessor: Clock configuration register (RCC_CFGR)
79
80You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
81
82See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:CFGR)
83
84For information about available fields see [`mod@cfgr`] module*/
85pub type CFGR = crate::Reg<cfgr::CFGRrs>;
86///Clock configuration register (RCC_CFGR)
87pub mod cfgr;
88/**CIR (rw) register accessor: Clock interrupt register (RCC_CIR)
89
90You can [`read`](crate::Reg::read) this register and get [`cir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
91
92See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:CIR)
93
94For information about available fields see [`mod@cir`] module*/
95pub type CIR = crate::Reg<cir::CIRrs>;
96///Clock interrupt register (RCC_CIR)
97pub mod cir;
98/**APB2RSTR (rw) register accessor: APB2 peripheral reset register (RCC_APB2RSTR)
99
100You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
101
102See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:APB2RSTR)
103
104For information about available fields see [`mod@apb2rstr`] module*/
105pub type APB2RSTR = crate::Reg<apb2rstr::APB2RSTRrs>;
106///APB2 peripheral reset register (RCC_APB2RSTR)
107pub mod apb2rstr;
108/**APB1RSTR (rw) register accessor: APB1 peripheral reset register (RCC_APB1RSTR)
109
110You can [`read`](crate::Reg::read) this register and get [`apb1rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
111
112See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:APB1RSTR)
113
114For information about available fields see [`mod@apb1rstr`] module*/
115pub type APB1RSTR = crate::Reg<apb1rstr::APB1RSTRrs>;
116///APB1 peripheral reset register (RCC_APB1RSTR)
117pub mod apb1rstr;
118/**AHBENR (rw) register accessor: AHB Peripheral Clock enable register (RCC_AHBENR)
119
120You can [`read`](crate::Reg::read) this register and get [`ahbenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:AHBENR)
123
124For information about available fields see [`mod@ahbenr`] module*/
125pub type AHBENR = crate::Reg<ahbenr::AHBENRrs>;
126///AHB Peripheral Clock enable register (RCC_AHBENR)
127pub mod ahbenr;
128/**APB2ENR (rw) register accessor: APB2 peripheral clock enable register (RCC_APB2ENR)
129
130You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
131
132See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:APB2ENR)
133
134For information about available fields see [`mod@apb2enr`] module*/
135pub type APB2ENR = crate::Reg<apb2enr::APB2ENRrs>;
136///APB2 peripheral clock enable register (RCC_APB2ENR)
137pub mod apb2enr;
138/**APB1ENR (rw) register accessor: APB1 peripheral clock enable register (RCC_APB1ENR)
139
140You can [`read`](crate::Reg::read) this register and get [`apb1enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
141
142See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:APB1ENR)
143
144For information about available fields see [`mod@apb1enr`] module*/
145pub type APB1ENR = crate::Reg<apb1enr::APB1ENRrs>;
146///APB1 peripheral clock enable register (RCC_APB1ENR)
147pub mod apb1enr;
148/**BDCR (rw) register accessor: Backup domain control register (RCC_BDCR)
149
150You can [`read`](crate::Reg::read) this register and get [`bdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
151
152See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:BDCR)
153
154For information about available fields see [`mod@bdcr`] module*/
155pub type BDCR = crate::Reg<bdcr::BDCRrs>;
156///Backup domain control register (RCC_BDCR)
157pub mod bdcr;
158/**CSR (rw) register accessor: Control/status register (RCC_CSR)
159
160You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC:CSR)
163
164For information about available fields see [`mod@csr`] module*/
165pub type CSR = crate::Reg<csr::CSRrs>;
166///Control/status register (RCC_CSR)
167pub mod csr;
stm32f1_staging/stm32f103/rcc.rs

stm32f1_staging/stm32f103/
rcc.rs
