stm32f1_staging/stm32f103/
i2c1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x02],
7    cr2: CR2,
8    _reserved2: [u8; 0x02],
9    oar1: OAR1,
10    _reserved3: [u8; 0x02],
11    oar2: OAR2,
12    _reserved4: [u8; 0x02],
13    dr: DR,
14    _reserved5: [u8; 0x02],
15    sr1: SR1,
16    _reserved6: [u8; 0x02],
17    sr2: SR2,
18    _reserved7: [u8; 0x02],
19    ccr: CCR,
20    _reserved8: [u8; 0x02],
21    trise: TRISE,
22}
23impl RegisterBlock {
24    ///0x00 - Control register 1
25    #[inline(always)]
26    pub const fn cr1(&self) -> &CR1 {
27        &self.cr1
28    }
29    ///0x04 - Control register 2
30    #[inline(always)]
31    pub const fn cr2(&self) -> &CR2 {
32        &self.cr2
33    }
34    ///0x08 - Own address register 1
35    #[inline(always)]
36    pub const fn oar1(&self) -> &OAR1 {
37        &self.oar1
38    }
39    ///0x0c - Own address register 2
40    #[inline(always)]
41    pub const fn oar2(&self) -> &OAR2 {
42        &self.oar2
43    }
44    ///0x10 - Data register
45    #[inline(always)]
46    pub const fn dr(&self) -> &DR {
47        &self.dr
48    }
49    ///0x14 - Status register 1
50    #[inline(always)]
51    pub const fn sr1(&self) -> &SR1 {
52        &self.sr1
53    }
54    ///0x18 - Status register 2
55    #[inline(always)]
56    pub const fn sr2(&self) -> &SR2 {
57        &self.sr2
58    }
59    ///0x1c - Clock control register
60    #[inline(always)]
61    pub const fn ccr(&self) -> &CCR {
62        &self.ccr
63    }
64    ///0x20 - TRISE register
65    #[inline(always)]
66    pub const fn trise(&self) -> &TRISE {
67        &self.trise
68    }
69}
70/**CR1 (rw) register accessor: Control register 1
71
72You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
73
74See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:CR1)
75
76For information about available fields see [`mod@cr1`] module*/
77pub type CR1 = crate::Reg<cr1::CR1rs>;
78///Control register 1
79pub mod cr1;
80/**CR2 (rw) register accessor: Control register 2
81
82You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
83
84See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:CR2)
85
86For information about available fields see [`mod@cr2`] module*/
87pub type CR2 = crate::Reg<cr2::CR2rs>;
88///Control register 2
89pub mod cr2;
90/**OAR1 (rw) register accessor: Own address register 1
91
92You can [`read`](crate::Reg::read) this register and get [`oar1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:OAR1)
95
96For information about available fields see [`mod@oar1`] module*/
97pub type OAR1 = crate::Reg<oar1::OAR1rs>;
98///Own address register 1
99pub mod oar1;
100/**OAR2 (rw) register accessor: Own address register 2
101
102You can [`read`](crate::Reg::read) this register and get [`oar2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
103
104See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:OAR2)
105
106For information about available fields see [`mod@oar2`] module*/
107pub type OAR2 = crate::Reg<oar2::OAR2rs>;
108///Own address register 2
109pub mod oar2;
110/**DR (rw) register accessor: Data register
111
112You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
113
114See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:DR)
115
116For information about available fields see [`mod@dr`] module*/
117pub type DR = crate::Reg<dr::DRrs>;
118///Data register
119pub mod dr;
120/**SR1 (rw) register accessor: Status register 1
121
122You can [`read`](crate::Reg::read) this register and get [`sr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:SR1)
125
126For information about available fields see [`mod@sr1`] module*/
127pub type SR1 = crate::Reg<sr1::SR1rs>;
128///Status register 1
129pub mod sr1;
130/**SR2 (r) register accessor: Status register 2
131
132You can [`read`](crate::Reg::read) this register and get [`sr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:SR2)
135
136For information about available fields see [`mod@sr2`] module*/
137pub type SR2 = crate::Reg<sr2::SR2rs>;
138///Status register 2
139pub mod sr2;
140/**CCR (rw) register accessor: Clock control register
141
142You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:CCR)
145
146For information about available fields see [`mod@ccr`] module*/
147pub type CCR = crate::Reg<ccr::CCRrs>;
148///Clock control register
149pub mod ccr;
150/**TRISE (rw) register accessor: TRISE register
151
152You can [`read`](crate::Reg::read) this register and get [`trise::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trise::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:TRISE)
155
156For information about available fields see [`mod@trise`] module*/
157pub type TRISE = crate::Reg<trise::TRISErs>;
158///TRISE register
159pub mod trise;
stm32f1_staging/stm32f103/i2c1.rs

stm32f1_staging/stm32f103/
i2c1.rs
