stm32f1_staging/stm32f103/flash/
acr.rs

1///Register `ACR` reader
2pub type R = crate::R<ACRrs>;
3///Register `ACR` writer
4pub type W = crate::W<ACRrs>;
5/**Latency
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum LATENCY {
12    ///0: Zero wait state, if 0 < SYSCLK≤ 24 MHz
13    Ws0 = 0,
14    ///1: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
15    Ws1 = 1,
16    ///2: Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
17    Ws2 = 2,
18}
19impl From<LATENCY> for u8 {
20    #[inline(always)]
21    fn from(variant: LATENCY) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for LATENCY {
26    type Ux = u8;
27}
28impl crate::IsEnum for LATENCY {}
29///Field `LATENCY` reader - Latency
30pub type LATENCY_R = crate::FieldReader<LATENCY>;
31impl LATENCY_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<LATENCY> {
35        match self.bits {
36            0 => Some(LATENCY::Ws0),
37            1 => Some(LATENCY::Ws1),
38            2 => Some(LATENCY::Ws2),
39            _ => None,
40        }
41    }
42    ///Zero wait state, if 0 < SYSCLK≤ 24 MHz
43    #[inline(always)]
44    pub fn is_ws0(&self) -> bool {
45        *self == LATENCY::Ws0
46    }
47    ///One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
48    #[inline(always)]
49    pub fn is_ws1(&self) -> bool {
50        *self == LATENCY::Ws1
51    }
52    ///Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
53    #[inline(always)]
54    pub fn is_ws2(&self) -> bool {
55        *self == LATENCY::Ws2
56    }
57}
58///Field `LATENCY` writer - Latency
59pub type LATENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 3, LATENCY>;
60impl<'a, REG> LATENCY_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///Zero wait state, if 0 < SYSCLK≤ 24 MHz
66    #[inline(always)]
67    pub fn ws0(self) -> &'a mut crate::W<REG> {
68        self.variant(LATENCY::Ws0)
69    }
70    ///One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
71    #[inline(always)]
72    pub fn ws1(self) -> &'a mut crate::W<REG> {
73        self.variant(LATENCY::Ws1)
74    }
75    ///Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
76    #[inline(always)]
77    pub fn ws2(self) -> &'a mut crate::W<REG> {
78        self.variant(LATENCY::Ws2)
79    }
80}
81///Field `HLFCYA` reader - Flash half cycle access enable
82pub type HLFCYA_R = crate::BitReader;
83///Field `HLFCYA` writer - Flash half cycle access enable
84pub type HLFCYA_W<'a, REG> = crate::BitWriter<'a, REG>;
85///Field `PRFTBE` reader - Prefetch buffer enable
86pub type PRFTBE_R = crate::BitReader;
87///Field `PRFTBE` writer - Prefetch buffer enable
88pub type PRFTBE_W<'a, REG> = crate::BitWriter<'a, REG>;
89///Field `PRFTBS` reader - Prefetch buffer status
90pub type PRFTBS_R = crate::BitReader;
91impl R {
92    ///Bits 0:2 - Latency
93    #[inline(always)]
94    pub fn latency(&self) -> LATENCY_R {
95        LATENCY_R::new((self.bits & 7) as u8)
96    }
97    ///Bit 3 - Flash half cycle access enable
98    #[inline(always)]
99    pub fn hlfcya(&self) -> HLFCYA_R {
100        HLFCYA_R::new(((self.bits >> 3) & 1) != 0)
101    }
102    ///Bit 4 - Prefetch buffer enable
103    #[inline(always)]
104    pub fn prftbe(&self) -> PRFTBE_R {
105        PRFTBE_R::new(((self.bits >> 4) & 1) != 0)
106    }
107    ///Bit 5 - Prefetch buffer status
108    #[inline(always)]
109    pub fn prftbs(&self) -> PRFTBS_R {
110        PRFTBS_R::new(((self.bits >> 5) & 1) != 0)
111    }
112}
113impl core::fmt::Debug for R {
114    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
115        f.debug_struct("ACR")
116            .field("latency", &self.latency())
117            .field("hlfcya", &self.hlfcya())
118            .field("prftbe", &self.prftbe())
119            .field("prftbs", &self.prftbs())
120            .finish()
121    }
122}
123impl W {
124    ///Bits 0:2 - Latency
125    #[inline(always)]
126    pub fn latency(&mut self) -> LATENCY_W<ACRrs> {
127        LATENCY_W::new(self, 0)
128    }
129    ///Bit 3 - Flash half cycle access enable
130    #[inline(always)]
131    pub fn hlfcya(&mut self) -> HLFCYA_W<ACRrs> {
132        HLFCYA_W::new(self, 3)
133    }
134    ///Bit 4 - Prefetch buffer enable
135    #[inline(always)]
136    pub fn prftbe(&mut self) -> PRFTBE_W<ACRrs> {
137        PRFTBE_W::new(self, 4)
138    }
139}
140/**Flash access control register
141
142You can [`read`](crate::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#FLASH:ACR)*/
145pub struct ACRrs;
146impl crate::RegisterSpec for ACRrs {
147    type Ux = u32;
148}
149///`read()` method returns [`acr::R`](R) reader structure
150impl crate::Readable for ACRrs {}
151///`write(|w| ..)` method takes [`acr::W`](W) writer structure
152impl crate::Writable for ACRrs {
153    type Safety = crate::Unsafe;
154}
155///`reset()` method sets ACR to value 0x30
156impl crate::Resettable for ACRrs {
157    const RESET_VALUE: u32 = 0x30;
158}
stm32f1_staging/stm32f103/flash/acr.rs

stm32f1_staging/stm32f103/flash/
acr.rs
