stm32f1_staging/stm32f103/dma1/
ifcr.rs

1///Register `IFCR` writer
2pub type W = crate::W<IFCRrs>;
3/**Channel %s Global interrupt clear
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum CGIF1 {
9    ///1: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
10    Clear = 1,
11}
12impl From<CGIF1> for bool {
13    #[inline(always)]
14    fn from(variant: CGIF1) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `CGIF(1-7)` writer - Channel %s Global interrupt clear
19pub type CGIF_W<'a, REG> = crate::BitWriter<'a, REG, CGIF1>;
20impl<'a, REG> CGIF_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(CGIF1::Clear)
28    }
29}
30/**Channel %s Transfer Complete clear
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum CTCIF1 {
36    ///1: Clears the TCIF flag in the ISR register
37    Clear = 1,
38}
39impl From<CTCIF1> for bool {
40    #[inline(always)]
41    fn from(variant: CTCIF1) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `CTCIF(1-7)` writer - Channel %s Transfer Complete clear
46pub type CTCIF_W<'a, REG> = crate::BitWriter<'a, REG, CTCIF1>;
47impl<'a, REG> CTCIF_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///Clears the TCIF flag in the ISR register
52    #[inline(always)]
53    pub fn clear(self) -> &'a mut crate::W<REG> {
54        self.variant(CTCIF1::Clear)
55    }
56}
57/**Channel %s Half Transfer clear
58
59Value on reset: 0*/
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CHTIF1 {
63    ///1: Clears the HTIF flag in the ISR register
64    Clear = 1,
65}
66impl From<CHTIF1> for bool {
67    #[inline(always)]
68    fn from(variant: CHTIF1) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `CHTIF(1-7)` writer - Channel %s Half Transfer clear
73pub type CHTIF_W<'a, REG> = crate::BitWriter<'a, REG, CHTIF1>;
74impl<'a, REG> CHTIF_W<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77{
78    ///Clears the HTIF flag in the ISR register
79    #[inline(always)]
80    pub fn clear(self) -> &'a mut crate::W<REG> {
81        self.variant(CHTIF1::Clear)
82    }
83}
84/**Channel %s Transfer Error clear
85
86Value on reset: 0*/
87#[cfg_attr(feature = "defmt", derive(defmt::Format))]
88#[derive(Clone, Copy, Debug, PartialEq, Eq)]
89pub enum CTEIF1 {
90    ///1: Clears the TEIF flag in the ISR register
91    Clear = 1,
92}
93impl From<CTEIF1> for bool {
94    #[inline(always)]
95    fn from(variant: CTEIF1) -> Self {
96        variant as u8 != 0
97    }
98}
99///Field `CTEIF(1-7)` writer - Channel %s Transfer Error clear
100pub type CTEIF_W<'a, REG> = crate::BitWriter<'a, REG, CTEIF1>;
101impl<'a, REG> CTEIF_W<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104{
105    ///Clears the TEIF flag in the ISR register
106    #[inline(always)]
107    pub fn clear(self) -> &'a mut crate::W<REG> {
108        self.variant(CTEIF1::Clear)
109    }
110}
111impl core::fmt::Debug for crate::generic::Reg<IFCRrs> {
112    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
113        write!(f, "(not readable)")
114    }
115}
116impl W {
117    ///Channel (1-7) Global interrupt clear
118    ///
119    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CGIF1` field.</div>
120    #[inline(always)]
121    pub fn cgif(&mut self, n: u8) -> CGIF_W<IFCRrs> {
122        #[allow(clippy::no_effect)] [(); 7][n as usize];
123        CGIF_W::new(self, n * 4)
124    }
125    ///Bit 0 - Channel 1 Global interrupt clear
126    #[inline(always)]
127    pub fn cgif1(&mut self) -> CGIF_W<IFCRrs> {
128        CGIF_W::new(self, 0)
129    }
130    ///Bit 4 - Channel 2 Global interrupt clear
131    #[inline(always)]
132    pub fn cgif2(&mut self) -> CGIF_W<IFCRrs> {
133        CGIF_W::new(self, 4)
134    }
135    ///Bit 8 - Channel 3 Global interrupt clear
136    #[inline(always)]
137    pub fn cgif3(&mut self) -> CGIF_W<IFCRrs> {
138        CGIF_W::new(self, 8)
139    }
140    ///Bit 12 - Channel 4 Global interrupt clear
141    #[inline(always)]
142    pub fn cgif4(&mut self) -> CGIF_W<IFCRrs> {
143        CGIF_W::new(self, 12)
144    }
145    ///Bit 16 - Channel 5 Global interrupt clear
146    #[inline(always)]
147    pub fn cgif5(&mut self) -> CGIF_W<IFCRrs> {
148        CGIF_W::new(self, 16)
149    }
150    ///Bit 20 - Channel 6 Global interrupt clear
151    #[inline(always)]
152    pub fn cgif6(&mut self) -> CGIF_W<IFCRrs> {
153        CGIF_W::new(self, 20)
154    }
155    ///Bit 24 - Channel 7 Global interrupt clear
156    #[inline(always)]
157    pub fn cgif7(&mut self) -> CGIF_W<IFCRrs> {
158        CGIF_W::new(self, 24)
159    }
160    ///Channel (1-7) Transfer Complete clear
161    ///
162    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CTCIF1` field.</div>
163    #[inline(always)]
164    pub fn ctcif(&mut self, n: u8) -> CTCIF_W<IFCRrs> {
165        #[allow(clippy::no_effect)] [(); 7][n as usize];
166        CTCIF_W::new(self, n * 4 + 1)
167    }
168    ///Bit 1 - Channel 1 Transfer Complete clear
169    #[inline(always)]
170    pub fn ctcif1(&mut self) -> CTCIF_W<IFCRrs> {
171        CTCIF_W::new(self, 1)
172    }
173    ///Bit 5 - Channel 2 Transfer Complete clear
174    #[inline(always)]
175    pub fn ctcif2(&mut self) -> CTCIF_W<IFCRrs> {
176        CTCIF_W::new(self, 5)
177    }
178    ///Bit 9 - Channel 3 Transfer Complete clear
179    #[inline(always)]
180    pub fn ctcif3(&mut self) -> CTCIF_W<IFCRrs> {
181        CTCIF_W::new(self, 9)
182    }
183    ///Bit 13 - Channel 4 Transfer Complete clear
184    #[inline(always)]
185    pub fn ctcif4(&mut self) -> CTCIF_W<IFCRrs> {
186        CTCIF_W::new(self, 13)
187    }
188    ///Bit 17 - Channel 5 Transfer Complete clear
189    #[inline(always)]
190    pub fn ctcif5(&mut self) -> CTCIF_W<IFCRrs> {
191        CTCIF_W::new(self, 17)
192    }
193    ///Bit 21 - Channel 6 Transfer Complete clear
194    #[inline(always)]
195    pub fn ctcif6(&mut self) -> CTCIF_W<IFCRrs> {
196        CTCIF_W::new(self, 21)
197    }
198    ///Bit 25 - Channel 7 Transfer Complete clear
199    #[inline(always)]
200    pub fn ctcif7(&mut self) -> CTCIF_W<IFCRrs> {
201        CTCIF_W::new(self, 25)
202    }
203    ///Channel (1-7) Half Transfer clear
204    ///
205    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CHTIF1` field.</div>
206    #[inline(always)]
207    pub fn chtif(&mut self, n: u8) -> CHTIF_W<IFCRrs> {
208        #[allow(clippy::no_effect)] [(); 7][n as usize];
209        CHTIF_W::new(self, n * 4 + 2)
210    }
211    ///Bit 2 - Channel 1 Half Transfer clear
212    #[inline(always)]
213    pub fn chtif1(&mut self) -> CHTIF_W<IFCRrs> {
214        CHTIF_W::new(self, 2)
215    }
216    ///Bit 6 - Channel 2 Half Transfer clear
217    #[inline(always)]
218    pub fn chtif2(&mut self) -> CHTIF_W<IFCRrs> {
219        CHTIF_W::new(self, 6)
220    }
221    ///Bit 10 - Channel 3 Half Transfer clear
222    #[inline(always)]
223    pub fn chtif3(&mut self) -> CHTIF_W<IFCRrs> {
224        CHTIF_W::new(self, 10)
225    }
226    ///Bit 14 - Channel 4 Half Transfer clear
227    #[inline(always)]
228    pub fn chtif4(&mut self) -> CHTIF_W<IFCRrs> {
229        CHTIF_W::new(self, 14)
230    }
231    ///Bit 18 - Channel 5 Half Transfer clear
232    #[inline(always)]
233    pub fn chtif5(&mut self) -> CHTIF_W<IFCRrs> {
234        CHTIF_W::new(self, 18)
235    }
236    ///Bit 22 - Channel 6 Half Transfer clear
237    #[inline(always)]
238    pub fn chtif6(&mut self) -> CHTIF_W<IFCRrs> {
239        CHTIF_W::new(self, 22)
240    }
241    ///Bit 26 - Channel 7 Half Transfer clear
242    #[inline(always)]
243    pub fn chtif7(&mut self) -> CHTIF_W<IFCRrs> {
244        CHTIF_W::new(self, 26)
245    }
246    ///Channel (1-7) Transfer Error clear
247    ///
248    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CTEIF1` field.</div>
249    #[inline(always)]
250    pub fn cteif(&mut self, n: u8) -> CTEIF_W<IFCRrs> {
251        #[allow(clippy::no_effect)] [(); 7][n as usize];
252        CTEIF_W::new(self, n * 4 + 3)
253    }
254    ///Bit 3 - Channel 1 Transfer Error clear
255    #[inline(always)]
256    pub fn cteif1(&mut self) -> CTEIF_W<IFCRrs> {
257        CTEIF_W::new(self, 3)
258    }
259    ///Bit 7 - Channel 2 Transfer Error clear
260    #[inline(always)]
261    pub fn cteif2(&mut self) -> CTEIF_W<IFCRrs> {
262        CTEIF_W::new(self, 7)
263    }
264    ///Bit 11 - Channel 3 Transfer Error clear
265    #[inline(always)]
266    pub fn cteif3(&mut self) -> CTEIF_W<IFCRrs> {
267        CTEIF_W::new(self, 11)
268    }
269    ///Bit 15 - Channel 4 Transfer Error clear
270    #[inline(always)]
271    pub fn cteif4(&mut self) -> CTEIF_W<IFCRrs> {
272        CTEIF_W::new(self, 15)
273    }
274    ///Bit 19 - Channel 5 Transfer Error clear
275    #[inline(always)]
276    pub fn cteif5(&mut self) -> CTEIF_W<IFCRrs> {
277        CTEIF_W::new(self, 19)
278    }
279    ///Bit 23 - Channel 6 Transfer Error clear
280    #[inline(always)]
281    pub fn cteif6(&mut self) -> CTEIF_W<IFCRrs> {
282        CTEIF_W::new(self, 23)
283    }
284    ///Bit 27 - Channel 7 Transfer Error clear
285    #[inline(always)]
286    pub fn cteif7(&mut self) -> CTEIF_W<IFCRrs> {
287        CTEIF_W::new(self, 27)
288    }
289}
290/**DMA interrupt flag clear register (DMA_IFCR)
291
292You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
293
294See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DMA1:IFCR)*/
295pub struct IFCRrs;
296impl crate::RegisterSpec for IFCRrs {
297    type Ux = u32;
298}
299///`write(|w| ..)` method takes [`ifcr::W`](W) writer structure
300impl crate::Writable for IFCRrs {
301    type Safety = crate::Unsafe;
302}
303///`reset()` method sets IFCR to value 0
304impl crate::Resettable for IFCRrs {}
stm32f1_staging/stm32f103/dma1/ifcr.rs

stm32f1_staging/stm32f103/dma1/
ifcr.rs
