stm32f1_staging/stm32f102/sdio/
sta.rs

1///Register `STA` reader
2pub type R = crate::R<STArs>;
3///Field `CCRCFAIL` reader - Command response received (CRC check failed)
4pub type CCRCFAIL_R = crate::BitReader;
5///Field `DCRCFAIL` reader - Data block sent/received (CRC check failed)
6pub type DCRCFAIL_R = crate::BitReader;
7///Field `CTIMEOUT` reader - Command response timeout
8pub type CTIMEOUT_R = crate::BitReader;
9///Field `DTIMEOUT` reader - Data timeout
10pub type DTIMEOUT_R = crate::BitReader;
11///Field `TXUNDERR` reader - Transmit FIFO underrun error
12pub type TXUNDERR_R = crate::BitReader;
13///Field `RXOVERR` reader - Received FIFO overrun error
14pub type RXOVERR_R = crate::BitReader;
15///Field `CMDREND` reader - Command response received (CRC check passed)
16pub type CMDREND_R = crate::BitReader;
17///Field `CMDSENT` reader - Command sent (no response required)
18pub type CMDSENT_R = crate::BitReader;
19///Field `DATAEND` reader - Data end (data counter, SDIDCOUNT, is zero)
20pub type DATAEND_R = crate::BitReader;
21///Field `STBITERR` reader - Start bit not detected on all data signals in wide bus mode
22pub type STBITERR_R = crate::BitReader;
23///Field `DBCKEND` reader - Data block sent/received (CRC check passed)
24pub type DBCKEND_R = crate::BitReader;
25///Field `CMDACT` reader - Command transfer in progress
26pub type CMDACT_R = crate::BitReader;
27///Field `TXACT` reader - Data transmit in progress
28pub type TXACT_R = crate::BitReader;
29///Field `RXACT` reader - Data receive in progress
30pub type RXACT_R = crate::BitReader;
31///Field `TXFIFOHE` reader - Transmit FIFO half empty: at least 8 words can be written into the FIFO
32pub type TXFIFOHE_R = crate::BitReader;
33///Field `RXFIFOHF` reader - Receive FIFO half full: there are at least 8 words in the FIFO
34pub type RXFIFOHF_R = crate::BitReader;
35///Field `TXFIFOF` reader - Transmit FIFO full
36pub type TXFIFOF_R = crate::BitReader;
37///Field `RXFIFOF` reader - Receive FIFO full
38pub type RXFIFOF_R = crate::BitReader;
39///Field `TXFIFOE` reader - Transmit FIFO empty
40pub type TXFIFOE_R = crate::BitReader;
41///Field `RXFIFOE` reader - Receive FIFO empty
42pub type RXFIFOE_R = crate::BitReader;
43///Field `TXDAVL` reader - Data available in transmit FIFO
44pub type TXDAVL_R = crate::BitReader;
45///Field `RXDAVL` reader - Data available in receive FIFO
46pub type RXDAVL_R = crate::BitReader;
47///Field `SDIOIT` reader - SDIO interrupt received
48pub type SDIOIT_R = crate::BitReader;
49///Field `CEATAEND` reader - CE-ATA command completion signal received for CMD61
50pub type CEATAEND_R = crate::BitReader;
51impl R {
52    ///Bit 0 - Command response received (CRC check failed)
53    #[inline(always)]
54    pub fn ccrcfail(&self) -> CCRCFAIL_R {
55        CCRCFAIL_R::new((self.bits & 1) != 0)
56    }
57    ///Bit 1 - Data block sent/received (CRC check failed)
58    #[inline(always)]
59    pub fn dcrcfail(&self) -> DCRCFAIL_R {
60        DCRCFAIL_R::new(((self.bits >> 1) & 1) != 0)
61    }
62    ///Bit 2 - Command response timeout
63    #[inline(always)]
64    pub fn ctimeout(&self) -> CTIMEOUT_R {
65        CTIMEOUT_R::new(((self.bits >> 2) & 1) != 0)
66    }
67    ///Bit 3 - Data timeout
68    #[inline(always)]
69    pub fn dtimeout(&self) -> DTIMEOUT_R {
70        DTIMEOUT_R::new(((self.bits >> 3) & 1) != 0)
71    }
72    ///Bit 4 - Transmit FIFO underrun error
73    #[inline(always)]
74    pub fn txunderr(&self) -> TXUNDERR_R {
75        TXUNDERR_R::new(((self.bits >> 4) & 1) != 0)
76    }
77    ///Bit 5 - Received FIFO overrun error
78    #[inline(always)]
79    pub fn rxoverr(&self) -> RXOVERR_R {
80        RXOVERR_R::new(((self.bits >> 5) & 1) != 0)
81    }
82    ///Bit 6 - Command response received (CRC check passed)
83    #[inline(always)]
84    pub fn cmdrend(&self) -> CMDREND_R {
85        CMDREND_R::new(((self.bits >> 6) & 1) != 0)
86    }
87    ///Bit 7 - Command sent (no response required)
88    #[inline(always)]
89    pub fn cmdsent(&self) -> CMDSENT_R {
90        CMDSENT_R::new(((self.bits >> 7) & 1) != 0)
91    }
92    ///Bit 8 - Data end (data counter, SDIDCOUNT, is zero)
93    #[inline(always)]
94    pub fn dataend(&self) -> DATAEND_R {
95        DATAEND_R::new(((self.bits >> 8) & 1) != 0)
96    }
97    ///Bit 9 - Start bit not detected on all data signals in wide bus mode
98    #[inline(always)]
99    pub fn stbiterr(&self) -> STBITERR_R {
100        STBITERR_R::new(((self.bits >> 9) & 1) != 0)
101    }
102    ///Bit 10 - Data block sent/received (CRC check passed)
103    #[inline(always)]
104    pub fn dbckend(&self) -> DBCKEND_R {
105        DBCKEND_R::new(((self.bits >> 10) & 1) != 0)
106    }
107    ///Bit 11 - Command transfer in progress
108    #[inline(always)]
109    pub fn cmdact(&self) -> CMDACT_R {
110        CMDACT_R::new(((self.bits >> 11) & 1) != 0)
111    }
112    ///Bit 12 - Data transmit in progress
113    #[inline(always)]
114    pub fn txact(&self) -> TXACT_R {
115        TXACT_R::new(((self.bits >> 12) & 1) != 0)
116    }
117    ///Bit 13 - Data receive in progress
118    #[inline(always)]
119    pub fn rxact(&self) -> RXACT_R {
120        RXACT_R::new(((self.bits >> 13) & 1) != 0)
121    }
122    ///Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO
123    #[inline(always)]
124    pub fn txfifohe(&self) -> TXFIFOHE_R {
125        TXFIFOHE_R::new(((self.bits >> 14) & 1) != 0)
126    }
127    ///Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO
128    #[inline(always)]
129    pub fn rxfifohf(&self) -> RXFIFOHF_R {
130        RXFIFOHF_R::new(((self.bits >> 15) & 1) != 0)
131    }
132    ///Bit 16 - Transmit FIFO full
133    #[inline(always)]
134    pub fn txfifof(&self) -> TXFIFOF_R {
135        TXFIFOF_R::new(((self.bits >> 16) & 1) != 0)
136    }
137    ///Bit 17 - Receive FIFO full
138    #[inline(always)]
139    pub fn rxfifof(&self) -> RXFIFOF_R {
140        RXFIFOF_R::new(((self.bits >> 17) & 1) != 0)
141    }
142    ///Bit 18 - Transmit FIFO empty
143    #[inline(always)]
144    pub fn txfifoe(&self) -> TXFIFOE_R {
145        TXFIFOE_R::new(((self.bits >> 18) & 1) != 0)
146    }
147    ///Bit 19 - Receive FIFO empty
148    #[inline(always)]
149    pub fn rxfifoe(&self) -> RXFIFOE_R {
150        RXFIFOE_R::new(((self.bits >> 19) & 1) != 0)
151    }
152    ///Bit 20 - Data available in transmit FIFO
153    #[inline(always)]
154    pub fn txdavl(&self) -> TXDAVL_R {
155        TXDAVL_R::new(((self.bits >> 20) & 1) != 0)
156    }
157    ///Bit 21 - Data available in receive FIFO
158    #[inline(always)]
159    pub fn rxdavl(&self) -> RXDAVL_R {
160        RXDAVL_R::new(((self.bits >> 21) & 1) != 0)
161    }
162    ///Bit 22 - SDIO interrupt received
163    #[inline(always)]
164    pub fn sdioit(&self) -> SDIOIT_R {
165        SDIOIT_R::new(((self.bits >> 22) & 1) != 0)
166    }
167    ///Bit 23 - CE-ATA command completion signal received for CMD61
168    #[inline(always)]
169    pub fn ceataend(&self) -> CEATAEND_R {
170        CEATAEND_R::new(((self.bits >> 23) & 1) != 0)
171    }
172}
173impl core::fmt::Debug for R {
174    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
175        f.debug_struct("STA")
176            .field("ceataend", &self.ceataend())
177            .field("sdioit", &self.sdioit())
178            .field("rxdavl", &self.rxdavl())
179            .field("txdavl", &self.txdavl())
180            .field("rxfifoe", &self.rxfifoe())
181            .field("txfifoe", &self.txfifoe())
182            .field("rxfifof", &self.rxfifof())
183            .field("txfifof", &self.txfifof())
184            .field("rxfifohf", &self.rxfifohf())
185            .field("txfifohe", &self.txfifohe())
186            .field("rxact", &self.rxact())
187            .field("txact", &self.txact())
188            .field("cmdact", &self.cmdact())
189            .field("dbckend", &self.dbckend())
190            .field("stbiterr", &self.stbiterr())
191            .field("dataend", &self.dataend())
192            .field("cmdsent", &self.cmdsent())
193            .field("cmdrend", &self.cmdrend())
194            .field("rxoverr", &self.rxoverr())
195            .field("txunderr", &self.txunderr())
196            .field("dtimeout", &self.dtimeout())
197            .field("ctimeout", &self.ctimeout())
198            .field("dcrcfail", &self.dcrcfail())
199            .field("ccrcfail", &self.ccrcfail())
200            .finish()
201    }
202}
203/**status register
204
205You can [`read`](crate::Reg::read) this register and get [`sta::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
206
207See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SDIO:STA)*/
208pub struct STArs;
209impl crate::RegisterSpec for STArs {
210    type Ux = u32;
211}
212///`read()` method returns [`sta::R`](R) reader structure
213impl crate::Readable for STArs {}
214///`reset()` method sets STA to value 0
215impl crate::Resettable for STArs {}
stm32f1_staging/stm32f102/sdio/sta.rs

stm32f1_staging/stm32f102/sdio/
sta.rs
