stm32f1_staging/stm32f101/
tim6.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    _reserved2: [u8; 0x04],
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved5: [u8; 0x0c],
12    cnt: CNT,
13    psc: PSC,
14    arr: ARR,
15}
16impl RegisterBlock {
17    ///0x00 - control register 1
18    #[inline(always)]
19    pub const fn cr1(&self) -> &CR1 {
20        &self.cr1
21    }
22    ///0x04 - control register 2
23    #[inline(always)]
24    pub const fn cr2(&self) -> &CR2 {
25        &self.cr2
26    }
27    ///0x0c - DMA/Interrupt enable register
28    #[inline(always)]
29    pub const fn dier(&self) -> &DIER {
30        &self.dier
31    }
32    ///0x10 - status register
33    #[inline(always)]
34    pub const fn sr(&self) -> &SR {
35        &self.sr
36    }
37    ///0x14 - event generation register
38    #[inline(always)]
39    pub const fn egr(&self) -> &EGR {
40        &self.egr
41    }
42    ///0x24 - counter
43    #[inline(always)]
44    pub const fn cnt(&self) -> &CNT {
45        &self.cnt
46    }
47    ///0x28 - prescaler
48    #[inline(always)]
49    pub const fn psc(&self) -> &PSC {
50        &self.psc
51    }
52    ///0x2c - auto-reload register
53    #[inline(always)]
54    pub const fn arr(&self) -> &ARR {
55        &self.arr
56    }
57}
58/**CR1 (rw) register accessor: control register 1
59
60You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
61
62See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:CR1)
63
64For information about available fields see [`mod@cr1`] module*/
65pub type CR1 = crate::Reg<cr1::CR1rs>;
66///control register 1
67pub mod cr1;
68/**CR2 (rw) register accessor: control register 2
69
70You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
71
72See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:CR2)
73
74For information about available fields see [`mod@cr2`] module*/
75pub type CR2 = crate::Reg<cr2::CR2rs>;
76///control register 2
77pub mod cr2;
78/**DIER (rw) register accessor: DMA/Interrupt enable register
79
80You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
81
82See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:DIER)
83
84For information about available fields see [`mod@dier`] module*/
85pub type DIER = crate::Reg<dier::DIERrs>;
86///DMA/Interrupt enable register
87pub mod dier;
88/**SR (rw) register accessor: status register
89
90You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
91
92See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:SR)
93
94For information about available fields see [`mod@sr`] module*/
95pub type SR = crate::Reg<sr::SRrs>;
96///status register
97pub mod sr;
98/**EGR (w) register accessor: event generation register
99
100You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
101
102See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:EGR)
103
104For information about available fields see [`mod@egr`] module*/
105pub type EGR = crate::Reg<egr::EGRrs>;
106///event generation register
107pub mod egr;
108/**CNT (rw) register accessor: counter
109
110You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
111
112See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:CNT)
113
114For information about available fields see [`mod@cnt`] module*/
115pub type CNT = crate::Reg<cnt::CNTrs>;
116///counter
117pub mod cnt;
118/**PSC (rw) register accessor: prescaler
119
120You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:PSC)
123
124For information about available fields see [`mod@psc`] module*/
125pub type PSC = crate::Reg<psc::PSCrs>;
126///prescaler
127pub mod psc;
128/**ARR (rw) register accessor: auto-reload register
129
130You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
131
132See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM6:ARR)
133
134For information about available fields see [`mod@arr`] module*/
135pub type ARR = crate::Reg<arr::ARRrs>;
136///auto-reload register
137pub mod arr;
stm32f1_staging/stm32f101/tim6.rs

stm32f1_staging/stm32f101/
tim6.rs
