stm32f1_staging/stm32f101/
fsmc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    bcr1: BCR1,
6    btr: (),
7    _reserved2: [u8; 0x04],
8    bcr: (),
9    _reserved3: [u8; 0x58],
10    pcr2: PCR2,
11    sr2: SR2,
12    pmem2: PMEM2,
13    patt2: PATT2,
14    _reserved7: [u8; 0x04],
15    eccr2: ECCR2,
16    _reserved8: [u8; 0x08],
17    pcr3: PCR3,
18    sr3: SR3,
19    pmem3: PMEM3,
20    patt3: PATT3,
21    _reserved12: [u8; 0x04],
22    eccr3: ECCR3,
23    _reserved13: [u8; 0x08],
24    pcr4: PCR4,
25    sr4: SR4,
26    pmem4: PMEM4,
27    patt4: PATT4,
28    pio4: PIO4,
29    _reserved18: [u8; 0x50],
30    bwtr: (),
31}
32impl RegisterBlock {
33    ///0x00 - SRAM/NOR-Flash chip-select control register 1
34    #[inline(always)]
35    pub const fn bcr1(&self) -> &BCR1 {
36        &self.bcr1
37    }
38    ///0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s
39    ///
40    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BTR1` register.</div>
41    #[inline(always)]
42    pub const fn btr(&self, n: usize) -> &BTR {
43        #[allow(clippy::no_effect)] [(); 4][n];
44        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(8 * n).cast() }
45    }
46    ///Iterator for array of:
47    ///0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s
48    #[inline(always)]
49    pub fn btr_iter(&self) -> impl Iterator<Item = &BTR> {
50        (0..4)
51            .map(move |n| unsafe {
52                &*core::ptr::from_ref(self).cast::<u8>().add(4).add(8 * n).cast()
53            })
54    }
55    ///0x04 - SRAM/NOR-Flash chip-select timing register 1
56    #[inline(always)]
57    pub const fn btr1(&self) -> &BTR {
58        self.btr(0)
59    }
60    ///0x0c - SRAM/NOR-Flash chip-select timing register 2
61    #[inline(always)]
62    pub const fn btr2(&self) -> &BTR {
63        self.btr(1)
64    }
65    ///0x14 - SRAM/NOR-Flash chip-select timing register 3
66    #[inline(always)]
67    pub const fn btr3(&self) -> &BTR {
68        self.btr(2)
69    }
70    ///0x1c - SRAM/NOR-Flash chip-select timing register 4
71    #[inline(always)]
72    pub const fn btr4(&self) -> &BTR {
73        self.btr(3)
74    }
75    ///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
76    ///
77    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BCR2` register.</div>
78    #[inline(always)]
79    pub const fn bcr(&self, n: usize) -> &BCR {
80        #[allow(clippy::no_effect)] [(); 3][n];
81        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(8 * n).cast() }
82    }
83    ///Iterator for array of:
84    ///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
85    #[inline(always)]
86    pub fn bcr_iter(&self) -> impl Iterator<Item = &BCR> {
87        (0..3)
88            .map(move |n| unsafe {
89                &*core::ptr::from_ref(self).cast::<u8>().add(8).add(8 * n).cast()
90            })
91    }
92    ///0x08 - SRAM/NOR-Flash chip-select control register 2
93    #[inline(always)]
94    pub const fn bcr2(&self) -> &BCR {
95        self.bcr(0)
96    }
97    ///0x10 - SRAM/NOR-Flash chip-select control register 3
98    #[inline(always)]
99    pub const fn bcr3(&self) -> &BCR {
100        self.bcr(1)
101    }
102    ///0x18 - SRAM/NOR-Flash chip-select control register 4
103    #[inline(always)]
104    pub const fn bcr4(&self) -> &BCR {
105        self.bcr(2)
106    }
107    ///0x60 - PC Card/NAND Flash control register 2
108    #[inline(always)]
109    pub const fn pcr2(&self) -> &PCR2 {
110        &self.pcr2
111    }
112    ///0x64 - FIFO status and interrupt register 2
113    #[inline(always)]
114    pub const fn sr2(&self) -> &SR2 {
115        &self.sr2
116    }
117    ///0x68 - Common memory space timing register 2
118    #[inline(always)]
119    pub const fn pmem2(&self) -> &PMEM2 {
120        &self.pmem2
121    }
122    ///0x6c - Attribute memory space timing register 2
123    #[inline(always)]
124    pub const fn patt2(&self) -> &PATT2 {
125        &self.patt2
126    }
127    ///0x74 - ECC result register 2
128    #[inline(always)]
129    pub const fn eccr2(&self) -> &ECCR2 {
130        &self.eccr2
131    }
132    ///0x80 - PC Card/NAND Flash control register 3
133    #[inline(always)]
134    pub const fn pcr3(&self) -> &PCR3 {
135        &self.pcr3
136    }
137    ///0x84 - FIFO status and interrupt register 3
138    #[inline(always)]
139    pub const fn sr3(&self) -> &SR3 {
140        &self.sr3
141    }
142    ///0x88 - Common memory space timing register 3
143    #[inline(always)]
144    pub const fn pmem3(&self) -> &PMEM3 {
145        &self.pmem3
146    }
147    ///0x8c - Attribute memory space timing register 3
148    #[inline(always)]
149    pub const fn patt3(&self) -> &PATT3 {
150        &self.patt3
151    }
152    ///0x94 - ECC result register 3
153    #[inline(always)]
154    pub const fn eccr3(&self) -> &ECCR3 {
155        &self.eccr3
156    }
157    ///0xa0 - PC Card/NAND Flash control register 4
158    #[inline(always)]
159    pub const fn pcr4(&self) -> &PCR4 {
160        &self.pcr4
161    }
162    ///0xa4 - FIFO status and interrupt register 4
163    #[inline(always)]
164    pub const fn sr4(&self) -> &SR4 {
165        &self.sr4
166    }
167    ///0xa8 - Common memory space timing register 4
168    #[inline(always)]
169    pub const fn pmem4(&self) -> &PMEM4 {
170        &self.pmem4
171    }
172    ///0xac - Attribute memory space timing register 4
173    #[inline(always)]
174    pub const fn patt4(&self) -> &PATT4 {
175        &self.patt4
176    }
177    ///0xb0 - I/O space timing register 4
178    #[inline(always)]
179    pub const fn pio4(&self) -> &PIO4 {
180        &self.pio4
181    }
182    ///0x104..0x114 - SRAM/NOR-Flash write timing registers %s
183    ///
184    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BWTR1` register.</div>
185    #[inline(always)]
186    pub const fn bwtr(&self, n: usize) -> &BWTR {
187        #[allow(clippy::no_effect)] [(); 4][n];
188        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(260).add(8 * n).cast() }
189    }
190    ///Iterator for array of:
191    ///0x104..0x114 - SRAM/NOR-Flash write timing registers %s
192    #[inline(always)]
193    pub fn bwtr_iter(&self) -> impl Iterator<Item = &BWTR> {
194        (0..4)
195            .map(move |n| unsafe {
196                &*core::ptr::from_ref(self).cast::<u8>().add(260).add(8 * n).cast()
197            })
198    }
199    ///0x104 - SRAM/NOR-Flash write timing registers 1
200    #[inline(always)]
201    pub const fn bwtr1(&self) -> &BWTR {
202        self.bwtr(0)
203    }
204    ///0x10c - SRAM/NOR-Flash write timing registers 2
205    #[inline(always)]
206    pub const fn bwtr2(&self) -> &BWTR {
207        self.bwtr(1)
208    }
209    ///0x114 - SRAM/NOR-Flash write timing registers 3
210    #[inline(always)]
211    pub const fn bwtr3(&self) -> &BWTR {
212        self.bwtr(2)
213    }
214    ///0x11c - SRAM/NOR-Flash write timing registers 4
215    #[inline(always)]
216    pub const fn bwtr4(&self) -> &BWTR {
217        self.bwtr(3)
218    }
219}
220/**BCR1 (rw) register accessor: SRAM/NOR-Flash chip-select control register 1
221
222You can [`read`](crate::Reg::read) this register and get [`bcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
223
224See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:BCR1)
225
226For information about available fields see [`mod@bcr1`] module*/
227pub type BCR1 = crate::Reg<bcr1::BCR1rs>;
228///SRAM/NOR-Flash chip-select control register 1
229pub mod bcr1;
230/**BTR (rw) register accessor: SRAM/NOR-Flash chip-select timing register %s
231
232You can [`read`](crate::Reg::read) this register and get [`btr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
233
234See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:BTR[1])
235
236For information about available fields see [`mod@btr`] module*/
237pub type BTR = crate::Reg<btr::BTRrs>;
238///SRAM/NOR-Flash chip-select timing register %s
239pub mod btr;
240/**BCR (rw) register accessor: SRAM/NOR-Flash chip-select control register %s
241
242You can [`read`](crate::Reg::read) this register and get [`bcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
243
244See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:BCR[2])
245
246For information about available fields see [`mod@bcr`] module*/
247pub type BCR = crate::Reg<bcr::BCRrs>;
248///SRAM/NOR-Flash chip-select control register %s
249pub mod bcr;
250/**PCR2 (rw) register accessor: PC Card/NAND Flash control register 2
251
252You can [`read`](crate::Reg::read) this register and get [`pcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
253
254See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PCR2)
255
256For information about available fields see [`mod@pcr2`] module*/
257pub type PCR2 = crate::Reg<pcr2::PCR2rs>;
258///PC Card/NAND Flash control register 2
259pub mod pcr2;
260/**SR2 (rw) register accessor: FIFO status and interrupt register 2
261
262You can [`read`](crate::Reg::read) this register and get [`sr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
263
264See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:SR2)
265
266For information about available fields see [`mod@sr2`] module*/
267pub type SR2 = crate::Reg<sr2::SR2rs>;
268///FIFO status and interrupt register 2
269pub mod sr2;
270/**PMEM2 (rw) register accessor: Common memory space timing register 2
271
272You can [`read`](crate::Reg::read) this register and get [`pmem2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
273
274See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PMEM2)
275
276For information about available fields see [`mod@pmem2`] module*/
277pub type PMEM2 = crate::Reg<pmem2::PMEM2rs>;
278///Common memory space timing register 2
279pub mod pmem2;
280/**PATT2 (rw) register accessor: Attribute memory space timing register 2
281
282You can [`read`](crate::Reg::read) this register and get [`patt2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
283
284See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PATT2)
285
286For information about available fields see [`mod@patt2`] module*/
287pub type PATT2 = crate::Reg<patt2::PATT2rs>;
288///Attribute memory space timing register 2
289pub mod patt2;
290/**ECCR2 (r) register accessor: ECC result register 2
291
292You can [`read`](crate::Reg::read) this register and get [`eccr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
293
294See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:ECCR2)
295
296For information about available fields see [`mod@eccr2`] module*/
297pub type ECCR2 = crate::Reg<eccr2::ECCR2rs>;
298///ECC result register 2
299pub mod eccr2;
300/**PCR3 (rw) register accessor: PC Card/NAND Flash control register 3
301
302You can [`read`](crate::Reg::read) this register and get [`pcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
303
304See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PCR3)
305
306For information about available fields see [`mod@pcr3`] module*/
307pub type PCR3 = crate::Reg<pcr3::PCR3rs>;
308///PC Card/NAND Flash control register 3
309pub mod pcr3;
310/**SR3 (rw) register accessor: FIFO status and interrupt register 3
311
312You can [`read`](crate::Reg::read) this register and get [`sr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
313
314See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:SR3)
315
316For information about available fields see [`mod@sr3`] module*/
317pub type SR3 = crate::Reg<sr3::SR3rs>;
318///FIFO status and interrupt register 3
319pub mod sr3;
320/**PMEM3 (rw) register accessor: Common memory space timing register 3
321
322You can [`read`](crate::Reg::read) this register and get [`pmem3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
323
324See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PMEM3)
325
326For information about available fields see [`mod@pmem3`] module*/
327pub type PMEM3 = crate::Reg<pmem3::PMEM3rs>;
328///Common memory space timing register 3
329pub mod pmem3;
330/**PATT3 (rw) register accessor: Attribute memory space timing register 3
331
332You can [`read`](crate::Reg::read) this register and get [`patt3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
333
334See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PATT3)
335
336For information about available fields see [`mod@patt3`] module*/
337pub type PATT3 = crate::Reg<patt3::PATT3rs>;
338///Attribute memory space timing register 3
339pub mod patt3;
340/**ECCR3 (r) register accessor: ECC result register 3
341
342You can [`read`](crate::Reg::read) this register and get [`eccr3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
343
344See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:ECCR3)
345
346For information about available fields see [`mod@eccr3`] module*/
347pub type ECCR3 = crate::Reg<eccr3::ECCR3rs>;
348///ECC result register 3
349pub mod eccr3;
350/**PCR4 (rw) register accessor: PC Card/NAND Flash control register 4
351
352You can [`read`](crate::Reg::read) this register and get [`pcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
353
354See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PCR4)
355
356For information about available fields see [`mod@pcr4`] module*/
357pub type PCR4 = crate::Reg<pcr4::PCR4rs>;
358///PC Card/NAND Flash control register 4
359pub mod pcr4;
360/**SR4 (rw) register accessor: FIFO status and interrupt register 4
361
362You can [`read`](crate::Reg::read) this register and get [`sr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
363
364See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:SR4)
365
366For information about available fields see [`mod@sr4`] module*/
367pub type SR4 = crate::Reg<sr4::SR4rs>;
368///FIFO status and interrupt register 4
369pub mod sr4;
370/**PMEM4 (rw) register accessor: Common memory space timing register 4
371
372You can [`read`](crate::Reg::read) this register and get [`pmem4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
373
374See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PMEM4)
375
376For information about available fields see [`mod@pmem4`] module*/
377pub type PMEM4 = crate::Reg<pmem4::PMEM4rs>;
378///Common memory space timing register 4
379pub mod pmem4;
380/**PATT4 (rw) register accessor: Attribute memory space timing register 4
381
382You can [`read`](crate::Reg::read) this register and get [`patt4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
383
384See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PATT4)
385
386For information about available fields see [`mod@patt4`] module*/
387pub type PATT4 = crate::Reg<patt4::PATT4rs>;
388///Attribute memory space timing register 4
389pub mod patt4;
390/**PIO4 (rw) register accessor: I/O space timing register 4
391
392You can [`read`](crate::Reg::read) this register and get [`pio4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
393
394See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:PIO4)
395
396For information about available fields see [`mod@pio4`] module*/
397pub type PIO4 = crate::Reg<pio4::PIO4rs>;
398///I/O space timing register 4
399pub mod pio4;
400/**BWTR (rw) register accessor: SRAM/NOR-Flash write timing registers %s
401
402You can [`read`](crate::Reg::read) this register and get [`bwtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
403
404See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#FSMC:BWTR[1])
405
406For information about available fields see [`mod@bwtr`] module*/
407pub type BWTR = crate::Reg<bwtr::BWTRrs>;
408///SRAM/NOR-Flash write timing registers %s
409pub mod bwtr;
stm32f1_staging/stm32f101/fsmc.rs

stm32f1_staging/stm32f101/
fsmc.rs
