stm32f1_staging/stm32f101/
ethernet_mmc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    mmccr: MMCCR,
6    mmcrir: MMCRIR,
7    mmctir: MMCTIR,
8    mmcrimr: MMCRIMR,
9    mmctimr: MMCTIMR,
10    _reserved5: [u8; 0x38],
11    mmctgfsccr: MMCTGFSCCR,
12    mmctgfmsccr: MMCTGFMSCCR,
13    _reserved7: [u8; 0x14],
14    mmctgfcr: MMCTGFCR,
15    _reserved8: [u8; 0x28],
16    mmcrfcecr: MMCRFCECR,
17    mmcrfaecr: MMCRFAECR,
18    _reserved10: [u8; 0x28],
19    mmcrgufcr: MMCRGUFCR,
20}
21impl RegisterBlock {
22    ///0x00 - Ethernet MMC control register (ETH_MMCCR)
23    #[inline(always)]
24    pub const fn mmccr(&self) -> &MMCCR {
25        &self.mmccr
26    }
27    ///0x04 - Ethernet MMC receive interrupt register (ETH_MMCRIR)
28    #[inline(always)]
29    pub const fn mmcrir(&self) -> &MMCRIR {
30        &self.mmcrir
31    }
32    ///0x08 - Ethernet MMC transmit interrupt register (ETH_MMCTIR)
33    #[inline(always)]
34    pub const fn mmctir(&self) -> &MMCTIR {
35        &self.mmctir
36    }
37    ///0x0c - Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
38    #[inline(always)]
39    pub const fn mmcrimr(&self) -> &MMCRIMR {
40        &self.mmcrimr
41    }
42    ///0x10 - Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
43    #[inline(always)]
44    pub const fn mmctimr(&self) -> &MMCTIMR {
45        &self.mmctimr
46    }
47    ///0x4c - Ethernet MMC transmitted good frames after a single collision counter
48    #[inline(always)]
49    pub const fn mmctgfsccr(&self) -> &MMCTGFSCCR {
50        &self.mmctgfsccr
51    }
52    ///0x50 - Ethernet MMC transmitted good frames after more than a single collision
53    #[inline(always)]
54    pub const fn mmctgfmsccr(&self) -> &MMCTGFMSCCR {
55        &self.mmctgfmsccr
56    }
57    ///0x68 - Ethernet MMC transmitted good frames counter register
58    #[inline(always)]
59    pub const fn mmctgfcr(&self) -> &MMCTGFCR {
60        &self.mmctgfcr
61    }
62    ///0x94 - Ethernet MMC received frames with CRC error counter register
63    #[inline(always)]
64    pub const fn mmcrfcecr(&self) -> &MMCRFCECR {
65        &self.mmcrfcecr
66    }
67    ///0x98 - Ethernet MMC received frames with alignment error counter register
68    #[inline(always)]
69    pub const fn mmcrfaecr(&self) -> &MMCRFAECR {
70        &self.mmcrfaecr
71    }
72    ///0xc4 - MMC received good unicast frames counter register
73    #[inline(always)]
74    pub const fn mmcrgufcr(&self) -> &MMCRGUFCR {
75        &self.mmcrgufcr
76    }
77}
78/**MMCCR (rw) register accessor: Ethernet MMC control register (ETH_MMCCR)
79
80You can [`read`](crate::Reg::read) this register and get [`mmccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
81
82See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCCR)
83
84For information about available fields see [`mod@mmccr`] module*/
85pub type MMCCR = crate::Reg<mmccr::MMCCRrs>;
86///Ethernet MMC control register (ETH_MMCCR)
87pub mod mmccr;
88/**MMCRIR (rw) register accessor: Ethernet MMC receive interrupt register (ETH_MMCRIR)
89
90You can [`read`](crate::Reg::read) this register and get [`mmcrir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmcrir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
91
92See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCRIR)
93
94For information about available fields see [`mod@mmcrir`] module*/
95pub type MMCRIR = crate::Reg<mmcrir::MMCRIRrs>;
96///Ethernet MMC receive interrupt register (ETH_MMCRIR)
97pub mod mmcrir;
98/**MMCTIR (rw) register accessor: Ethernet MMC transmit interrupt register (ETH_MMCTIR)
99
100You can [`read`](crate::Reg::read) this register and get [`mmctir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmctir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
101
102See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCTIR)
103
104For information about available fields see [`mod@mmctir`] module*/
105pub type MMCTIR = crate::Reg<mmctir::MMCTIRrs>;
106///Ethernet MMC transmit interrupt register (ETH_MMCTIR)
107pub mod mmctir;
108/**MMCRIMR (rw) register accessor: Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
109
110You can [`read`](crate::Reg::read) this register and get [`mmcrimr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmcrimr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
111
112See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCRIMR)
113
114For information about available fields see [`mod@mmcrimr`] module*/
115pub type MMCRIMR = crate::Reg<mmcrimr::MMCRIMRrs>;
116///Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
117pub mod mmcrimr;
118/**MMCTIMR (rw) register accessor: Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
119
120You can [`read`](crate::Reg::read) this register and get [`mmctimr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmctimr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCTIMR)
123
124For information about available fields see [`mod@mmctimr`] module*/
125pub type MMCTIMR = crate::Reg<mmctimr::MMCTIMRrs>;
126///Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
127pub mod mmctimr;
128/**MMCTGFSCCR (r) register accessor: Ethernet MMC transmitted good frames after a single collision counter
129
130You can [`read`](crate::Reg::read) this register and get [`mmctgfsccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
131
132See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCTGFSCCR)
133
134For information about available fields see [`mod@mmctgfsccr`] module*/
135pub type MMCTGFSCCR = crate::Reg<mmctgfsccr::MMCTGFSCCRrs>;
136///Ethernet MMC transmitted good frames after a single collision counter
137pub mod mmctgfsccr;
138/**MMCTGFMSCCR (r) register accessor: Ethernet MMC transmitted good frames after more than a single collision
139
140You can [`read`](crate::Reg::read) this register and get [`mmctgfmsccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
141
142See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCTGFMSCCR)
143
144For information about available fields see [`mod@mmctgfmsccr`] module*/
145pub type MMCTGFMSCCR = crate::Reg<mmctgfmsccr::MMCTGFMSCCRrs>;
146///Ethernet MMC transmitted good frames after more than a single collision
147pub mod mmctgfmsccr;
148/**MMCTGFCR (r) register accessor: Ethernet MMC transmitted good frames counter register
149
150You can [`read`](crate::Reg::read) this register and get [`mmctgfcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
151
152See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCTGFCR)
153
154For information about available fields see [`mod@mmctgfcr`] module*/
155pub type MMCTGFCR = crate::Reg<mmctgfcr::MMCTGFCRrs>;
156///Ethernet MMC transmitted good frames counter register
157pub mod mmctgfcr;
158/**MMCRFCECR (r) register accessor: Ethernet MMC received frames with CRC error counter register
159
160You can [`read`](crate::Reg::read) this register and get [`mmcrfcecr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCRFCECR)
163
164For information about available fields see [`mod@mmcrfcecr`] module*/
165pub type MMCRFCECR = crate::Reg<mmcrfcecr::MMCRFCECRrs>;
166///Ethernet MMC received frames with CRC error counter register
167pub mod mmcrfcecr;
168/**MMCRFAECR (r) register accessor: Ethernet MMC received frames with alignment error counter register
169
170You can [`read`](crate::Reg::read) this register and get [`mmcrfaecr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
171
172See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCRFAECR)
173
174For information about available fields see [`mod@mmcrfaecr`] module*/
175pub type MMCRFAECR = crate::Reg<mmcrfaecr::MMCRFAECRrs>;
176///Ethernet MMC received frames with alignment error counter register
177pub mod mmcrfaecr;
178/**MMCRGUFCR (r) register accessor: MMC received good unicast frames counter register
179
180You can [`read`](crate::Reg::read) this register and get [`mmcrgufcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
181
182See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#Ethernet_MMC:MMCRGUFCR)
183
184For information about available fields see [`mod@mmcrgufcr`] module*/
185pub type MMCRGUFCR = crate::Reg<mmcrgufcr::MMCRGUFCRrs>;
186///MMC received good unicast frames counter register
187pub mod mmcrgufcr;
stm32f1_staging/stm32f101/ethernet_mmc.rs

stm32f1_staging/stm32f101/
ethernet_mmc.rs
