stm32f1_staging/stm32f101/dma1/
ch.rs

1#[repr(C)]
2#[derive(Debug)]
3///Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
4pub struct CH {
5    cr: CR,
6    ndtr: NDTR,
7    par: PAR,
8    mar: MAR,
9    _reserved_end: [u8; 0x04],
10}
11impl CH {
12    ///0x00 - DMA channel configuration register (DMA_CCR)
13    #[inline(always)]
14    pub const fn cr(&self) -> &CR {
15        &self.cr
16    }
17    ///0x04 - DMA channel 1 number of data register
18    #[inline(always)]
19    pub const fn ndtr(&self) -> &NDTR {
20        &self.ndtr
21    }
22    ///0x08 - DMA channel 1 peripheral address register
23    #[inline(always)]
24    pub const fn par(&self) -> &PAR {
25        &self.par
26    }
27    ///0x0c - DMA channel 1 memory address register
28    #[inline(always)]
29    pub const fn mar(&self) -> &MAR {
30        &self.mar
31    }
32}
33/**CR (rw) register accessor: DMA channel configuration register (DMA_CCR)
34
35You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
36
37For information about available fields see [`mod@cr`] module*/
38pub type CR = crate::Reg<cr::CRrs>;
39///DMA channel configuration register (DMA_CCR)
40pub mod cr;
41/**NDTR (rw) register accessor: DMA channel 1 number of data register
42
43You can [`read`](crate::Reg::read) this register and get [`ndtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ndtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
44
45For information about available fields see [`mod@ndtr`] module*/
46pub type NDTR = crate::Reg<ndtr::NDTRrs>;
47///DMA channel 1 number of data register
48pub mod ndtr;
49/**PAR (rw) register accessor: DMA channel 1 peripheral address register
50
51You can [`read`](crate::Reg::read) this register and get [`par::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`par::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
52
53For information about available fields see [`mod@par`] module*/
54pub type PAR = crate::Reg<par::PARrs>;
55///DMA channel 1 peripheral address register
56pub mod par;
57/**MAR (rw) register accessor: DMA channel 1 memory address register
58
59You can [`read`](crate::Reg::read) this register and get [`mar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
60
61For information about available fields see [`mod@mar`] module*/
62pub type MAR = crate::Reg<mar::MARrs>;
63///DMA channel 1 memory address register
64pub mod mar;
stm32f1_staging/stm32f101/dma1/ch.rs

stm32f1_staging/stm32f101/dma1/
ch.rs
