stm32f1_staging/stm32f101/
dma1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    isr: ISR,
6    ifcr: IFCR,
7    ch: [CH; 7],
8}
9impl RegisterBlock {
10    ///0x00 - DMA interrupt status register (DMA_ISR)
11    #[inline(always)]
12    pub const fn isr(&self) -> &ISR {
13        &self.isr
14    }
15    ///0x04 - DMA interrupt flag clear register (DMA_IFCR)
16    #[inline(always)]
17    pub const fn ifcr(&self) -> &IFCR {
18        &self.ifcr
19    }
20    ///0x08..0x94 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
21    ///
22    ///<div class="warning">`n` is the index of cluster in the array. `n == 0` corresponds to `CH1` cluster.</div>
23    #[inline(always)]
24    pub const fn ch(&self, n: usize) -> &CH {
25        &self.ch[n]
26    }
27    ///Iterator for array of:
28    ///0x08..0x94 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
29    #[inline(always)]
30    pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
31        self.ch.iter()
32    }
33    ///0x08..0x1c - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
34    #[inline(always)]
35    pub const fn ch1(&self) -> &CH {
36        self.ch(0)
37    }
38    ///0x1c..0x30 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
39    #[inline(always)]
40    pub const fn ch2(&self) -> &CH {
41        self.ch(1)
42    }
43    ///0x30..0x44 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
44    #[inline(always)]
45    pub const fn ch3(&self) -> &CH {
46        self.ch(2)
47    }
48    ///0x44..0x58 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
49    #[inline(always)]
50    pub const fn ch4(&self) -> &CH {
51        self.ch(3)
52    }
53    ///0x58..0x6c - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
54    #[inline(always)]
55    pub const fn ch5(&self) -> &CH {
56        self.ch(4)
57    }
58    ///0x6c..0x80 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
59    #[inline(always)]
60    pub const fn ch6(&self) -> &CH {
61        self.ch(5)
62    }
63    ///0x80..0x94 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
64    #[inline(always)]
65    pub const fn ch7(&self) -> &CH {
66        self.ch(6)
67    }
68}
69/**ISR (r) register accessor: DMA interrupt status register (DMA_ISR)
70
71You can [`read`](crate::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
72
73See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DMA1:ISR)
74
75For information about available fields see [`mod@isr`] module*/
76pub type ISR = crate::Reg<isr::ISRrs>;
77///DMA interrupt status register (DMA_ISR)
78pub mod isr;
79/**IFCR (w) register accessor: DMA interrupt flag clear register (DMA_IFCR)
80
81You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
82
83See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DMA1:IFCR)
84
85For information about available fields see [`mod@ifcr`] module*/
86pub type IFCR = crate::Reg<ifcr::IFCRrs>;
87///DMA interrupt flag clear register (DMA_IFCR)
88pub mod ifcr;
89///Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
90pub use self::ch::CH;
91///Cluster
92///Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
93pub mod ch;
stm32f1_staging/stm32f101/dma1.rs

stm32f1_staging/stm32f101/
dma1.rs
