stm32f1_staging/stm32f101/
dac.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    swtrigr: SWTRIGR,
7    dhr12r1: DHR12R1,
8    dhr12l1: DHR12L1,
9    dhr8r1: DHR8R1,
10    dhr12r2: DHR12R2,
11    dhr12l2: DHR12L2,
12    dhr8r2: DHR8R2,
13    dhr12rd: DHR12RD,
14    dhr12ld: DHR12LD,
15    dhr8rd: DHR8RD,
16    dor1: DOR1,
17    dor2: DOR2,
18}
19impl RegisterBlock {
20    ///0x00 - Control register (DAC_CR)
21    #[inline(always)]
22    pub const fn cr(&self) -> &CR {
23        &self.cr
24    }
25    ///0x04 - DAC software trigger register (DAC_SWTRIGR)
26    #[inline(always)]
27    pub const fn swtrigr(&self) -> &SWTRIGR {
28        &self.swtrigr
29    }
30    ///0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
31    #[inline(always)]
32    pub const fn dhr12r1(&self) -> &DHR12R1 {
33        &self.dhr12r1
34    }
35    ///0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
36    #[inline(always)]
37    pub const fn dhr12l1(&self) -> &DHR12L1 {
38        &self.dhr12l1
39    }
40    ///0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
41    #[inline(always)]
42    pub const fn dhr8r1(&self) -> &DHR8R1 {
43        &self.dhr8r1
44    }
45    ///0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
46    #[inline(always)]
47    pub const fn dhr12r2(&self) -> &DHR12R2 {
48        &self.dhr12r2
49    }
50    ///0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
51    #[inline(always)]
52    pub const fn dhr12l2(&self) -> &DHR12L2 {
53        &self.dhr12l2
54    }
55    ///0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
56    #[inline(always)]
57    pub const fn dhr8r2(&self) -> &DHR8R2 {
58        &self.dhr8r2
59    }
60    ///0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
61    #[inline(always)]
62    pub const fn dhr12rd(&self) -> &DHR12RD {
63        &self.dhr12rd
64    }
65    ///0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
66    #[inline(always)]
67    pub const fn dhr12ld(&self) -> &DHR12LD {
68        &self.dhr12ld
69    }
70    ///0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
71    #[inline(always)]
72    pub const fn dhr8rd(&self) -> &DHR8RD {
73        &self.dhr8rd
74    }
75    ///0x2c - DAC channel1 data output register (DAC_DOR1)
76    #[inline(always)]
77    pub const fn dor1(&self) -> &DOR1 {
78        &self.dor1
79    }
80    ///0x30 - DAC channel2 data output register (DAC_DOR2)
81    #[inline(always)]
82    pub const fn dor2(&self) -> &DOR2 {
83        &self.dor2
84    }
85}
86/**CR (rw) register accessor: Control register (DAC_CR)
87
88You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
89
90See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:CR)
91
92For information about available fields see [`mod@cr`] module*/
93pub type CR = crate::Reg<cr::CRrs>;
94///Control register (DAC_CR)
95pub mod cr;
96/**SWTRIGR (w) register accessor: DAC software trigger register (DAC_SWTRIGR)
97
98You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrigr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
99
100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:SWTRIGR)
101
102For information about available fields see [`mod@swtrigr`] module*/
103pub type SWTRIGR = crate::Reg<swtrigr::SWTRIGRrs>;
104///DAC software trigger register (DAC_SWTRIGR)
105pub mod swtrigr;
106/**DHR12R1 (rw) register accessor: DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
107
108You can [`read`](crate::Reg::read) this register and get [`dhr12r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
109
110See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR12R1)
111
112For information about available fields see [`mod@dhr12r1`] module*/
113pub type DHR12R1 = crate::Reg<dhr12r1::DHR12R1rs>;
114///DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
115pub mod dhr12r1;
116/**DHR12L1 (rw) register accessor: DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
117
118You can [`read`](crate::Reg::read) this register and get [`dhr12l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
119
120See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR12L1)
121
122For information about available fields see [`mod@dhr12l1`] module*/
123pub type DHR12L1 = crate::Reg<dhr12l1::DHR12L1rs>;
124///DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
125pub mod dhr12l1;
126/**DHR8R1 (rw) register accessor: DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
127
128You can [`read`](crate::Reg::read) this register and get [`dhr8r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
129
130See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR8R1)
131
132For information about available fields see [`mod@dhr8r1`] module*/
133pub type DHR8R1 = crate::Reg<dhr8r1::DHR8R1rs>;
134///DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
135pub mod dhr8r1;
136/**DHR12R2 (rw) register accessor: DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
137
138You can [`read`](crate::Reg::read) this register and get [`dhr12r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
139
140See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR12R2)
141
142For information about available fields see [`mod@dhr12r2`] module*/
143pub type DHR12R2 = crate::Reg<dhr12r2::DHR12R2rs>;
144///DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
145pub mod dhr12r2;
146/**DHR12L2 (rw) register accessor: DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
147
148You can [`read`](crate::Reg::read) this register and get [`dhr12l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
149
150See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR12L2)
151
152For information about available fields see [`mod@dhr12l2`] module*/
153pub type DHR12L2 = crate::Reg<dhr12l2::DHR12L2rs>;
154///DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
155pub mod dhr12l2;
156/**DHR8R2 (rw) register accessor: DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
157
158You can [`read`](crate::Reg::read) this register and get [`dhr8r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
159
160See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR8R2)
161
162For information about available fields see [`mod@dhr8r2`] module*/
163pub type DHR8R2 = crate::Reg<dhr8r2::DHR8R2rs>;
164///DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
165pub mod dhr8r2;
166/**DHR12RD (rw) register accessor: Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
167
168You can [`read`](crate::Reg::read) this register and get [`dhr12rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
169
170See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR12RD)
171
172For information about available fields see [`mod@dhr12rd`] module*/
173pub type DHR12RD = crate::Reg<dhr12rd::DHR12RDrs>;
174///Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
175pub mod dhr12rd;
176/**DHR12LD (rw) register accessor: DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
177
178You can [`read`](crate::Reg::read) this register and get [`dhr12ld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12ld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
179
180See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR12LD)
181
182For information about available fields see [`mod@dhr12ld`] module*/
183pub type DHR12LD = crate::Reg<dhr12ld::DHR12LDrs>;
184///DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
185pub mod dhr12ld;
186/**DHR8RD (rw) register accessor: DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
187
188You can [`read`](crate::Reg::read) this register and get [`dhr8rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
189
190See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DHR8RD)
191
192For information about available fields see [`mod@dhr8rd`] module*/
193pub type DHR8RD = crate::Reg<dhr8rd::DHR8RDrs>;
194///DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
195pub mod dhr8rd;
196/**DOR1 (r) register accessor: DAC channel1 data output register (DAC_DOR1)
197
198You can [`read`](crate::Reg::read) this register and get [`dor1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
199
200See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DOR1)
201
202For information about available fields see [`mod@dor1`] module*/
203pub type DOR1 = crate::Reg<dor1::DOR1rs>;
204///DAC channel1 data output register (DAC_DOR1)
205pub mod dor1;
206/**DOR2 (r) register accessor: DAC channel2 data output register (DAC_DOR2)
207
208You can [`read`](crate::Reg::read) this register and get [`dor2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
209
210See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#DAC:DOR2)
211
212For information about available fields see [`mod@dor2`] module*/
213pub type DOR2 = crate::Reg<dor2::DOR2rs>;
214///DAC channel2 data output register (DAC_DOR2)
215pub mod dor2;
stm32f1_staging/stm32f101/dac.rs

stm32f1_staging/stm32f101/
dac.rs
