stm32f1_staging/stm32f101/
adc2.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    sr: SR,
6    cr1: CR1,
7    cr2: CR2,
8    smpr1: SMPR1,
9    smpr2: SMPR2,
10    jofr: [JOFR; 4],
11    htr: HTR,
12    ltr: LTR,
13    sqr1: SQR1,
14    sqr2: SQR2,
15    sqr3: SQR3,
16    jsqr: JSQR,
17    jdr: [JDR; 4],
18    dr: DR,
19}
20impl RegisterBlock {
21    ///0x00 - status register
22    #[inline(always)]
23    pub const fn sr(&self) -> &SR {
24        &self.sr
25    }
26    ///0x04 - control register 1
27    #[inline(always)]
28    pub const fn cr1(&self) -> &CR1 {
29        &self.cr1
30    }
31    ///0x08 - control register 2
32    #[inline(always)]
33    pub const fn cr2(&self) -> &CR2 {
34        &self.cr2
35    }
36    ///0x0c - sample time register 1
37    #[inline(always)]
38    pub const fn smpr1(&self) -> &SMPR1 {
39        &self.smpr1
40    }
41    ///0x10 - sample time register 2
42    #[inline(always)]
43    pub const fn smpr2(&self) -> &SMPR2 {
44        &self.smpr2
45    }
46    ///0x14..0x24 - injected channel data offset register %s
47    ///
48    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `JOFR1` register.</div>
49    #[inline(always)]
50    pub const fn jofr(&self, n: usize) -> &JOFR {
51        &self.jofr[n]
52    }
53    ///Iterator for array of:
54    ///0x14..0x24 - injected channel data offset register %s
55    #[inline(always)]
56    pub fn jofr_iter(&self) -> impl Iterator<Item = &JOFR> {
57        self.jofr.iter()
58    }
59    ///0x14 - injected channel data offset register 1
60    #[inline(always)]
61    pub const fn jofr1(&self) -> &JOFR {
62        self.jofr(0)
63    }
64    ///0x18 - injected channel data offset register 2
65    #[inline(always)]
66    pub const fn jofr2(&self) -> &JOFR {
67        self.jofr(1)
68    }
69    ///0x1c - injected channel data offset register 3
70    #[inline(always)]
71    pub const fn jofr3(&self) -> &JOFR {
72        self.jofr(2)
73    }
74    ///0x20 - injected channel data offset register 4
75    #[inline(always)]
76    pub const fn jofr4(&self) -> &JOFR {
77        self.jofr(3)
78    }
79    ///0x24 - watchdog higher threshold register
80    #[inline(always)]
81    pub const fn htr(&self) -> &HTR {
82        &self.htr
83    }
84    ///0x28 - watchdog lower threshold register
85    #[inline(always)]
86    pub const fn ltr(&self) -> &LTR {
87        &self.ltr
88    }
89    ///0x2c - regular sequence register 1
90    #[inline(always)]
91    pub const fn sqr1(&self) -> &SQR1 {
92        &self.sqr1
93    }
94    ///0x30 - regular sequence register 2
95    #[inline(always)]
96    pub const fn sqr2(&self) -> &SQR2 {
97        &self.sqr2
98    }
99    ///0x34 - regular sequence register 3
100    #[inline(always)]
101    pub const fn sqr3(&self) -> &SQR3 {
102        &self.sqr3
103    }
104    ///0x38 - injected sequence register
105    #[inline(always)]
106    pub const fn jsqr(&self) -> &JSQR {
107        &self.jsqr
108    }
109    ///0x3c..0x4c - injected data register x
110    ///
111    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `JDR1` register.</div>
112    #[inline(always)]
113    pub const fn jdr(&self, n: usize) -> &JDR {
114        &self.jdr[n]
115    }
116    ///Iterator for array of:
117    ///0x3c..0x4c - injected data register x
118    #[inline(always)]
119    pub fn jdr_iter(&self) -> impl Iterator<Item = &JDR> {
120        self.jdr.iter()
121    }
122    ///0x3c - injected data register x
123    #[inline(always)]
124    pub const fn jdr1(&self) -> &JDR {
125        self.jdr(0)
126    }
127    ///0x40 - injected data register x
128    #[inline(always)]
129    pub const fn jdr2(&self) -> &JDR {
130        self.jdr(1)
131    }
132    ///0x44 - injected data register x
133    #[inline(always)]
134    pub const fn jdr3(&self) -> &JDR {
135        self.jdr(2)
136    }
137    ///0x48 - injected data register x
138    #[inline(always)]
139    pub const fn jdr4(&self) -> &JDR {
140        self.jdr(3)
141    }
142    ///0x4c - regular data register
143    #[inline(always)]
144    pub const fn dr(&self) -> &DR {
145        &self.dr
146    }
147}
148pub use crate::stm32f101::adc1::sr;
149pub use crate::stm32f101::adc1::SR;
150/**CR1 (rw) register accessor: control register 1
151
152You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#ADC2:CR1)
155
156For information about available fields see [`mod@cr1`] module*/
157pub type CR1 = crate::Reg<cr1::CR1rs>;
158///control register 1
159pub mod cr1;
160pub use crate::stm32f101::adc1::cr2;
161pub use crate::stm32f101::adc1::htr;
162pub use crate::stm32f101::adc1::jdr;
163pub use crate::stm32f101::adc1::jofr;
164pub use crate::stm32f101::adc1::jsqr;
165pub use crate::stm32f101::adc1::ltr;
166pub use crate::stm32f101::adc1::smpr1;
167pub use crate::stm32f101::adc1::smpr2;
168pub use crate::stm32f101::adc1::sqr1;
169pub use crate::stm32f101::adc1::sqr2;
170pub use crate::stm32f101::adc1::sqr3;
171pub use crate::stm32f101::adc1::CR2;
172pub use crate::stm32f101::adc1::HTR;
173pub use crate::stm32f101::adc1::JDR;
174pub use crate::stm32f101::adc1::JOFR;
175pub use crate::stm32f101::adc1::JSQR;
176pub use crate::stm32f101::adc1::LTR;
177pub use crate::stm32f101::adc1::SMPR1;
178pub use crate::stm32f101::adc1::SMPR2;
179pub use crate::stm32f101::adc1::SQR1;
180pub use crate::stm32f101::adc1::SQR2;
181pub use crate::stm32f101::adc1::SQR3;
182/**DR (r) register accessor: regular data register
183
184You can [`read`](crate::Reg::read) this register and get [`dr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
185
186See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#ADC2:DR)
187
188For information about available fields see [`mod@dr`] module*/
189pub type DR = crate::Reg<dr::DRrs>;
190///regular data register
191pub mod dr;
stm32f1_staging/stm32f101/adc2.rs

stm32f1_staging/stm32f101/
adc2.rs
