stm32f1_staging/stm32f100/
tim13.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x08],
7    dier: DIER,
8    sr: SR,
9    egr: EGR,
10    _reserved_4_ccmr1: [u8; 0x04],
11    _reserved5: [u8; 0x04],
12    ccer: CCER,
13    cnt: CNT,
14    psc: PSC,
15    arr: ARR,
16    _reserved9: [u8; 0x04],
17    ccr: [CCR; 1],
18}
19impl RegisterBlock {
20    ///0x00 - control register 1
21    #[inline(always)]
22    pub const fn cr1(&self) -> &CR1 {
23        &self.cr1
24    }
25    ///0x0c - DMA/Interrupt enable register
26    #[inline(always)]
27    pub const fn dier(&self) -> &DIER {
28        &self.dier
29    }
30    ///0x10 - status register
31    #[inline(always)]
32    pub const fn sr(&self) -> &SR {
33        &self.sr
34    }
35    ///0x14 - event generation register
36    #[inline(always)]
37    pub const fn egr(&self) -> &EGR {
38        &self.egr
39    }
40    ///0x18 - capture/compare mode register (input mode)
41    #[inline(always)]
42    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
43        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
44    }
45    ///0x18 - capture/compare mode register (output mode)
46    #[inline(always)]
47    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
48        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
49    }
50    ///0x20 - capture/compare enable register
51    #[inline(always)]
52    pub const fn ccer(&self) -> &CCER {
53        &self.ccer
54    }
55    ///0x24 - counter
56    #[inline(always)]
57    pub const fn cnt(&self) -> &CNT {
58        &self.cnt
59    }
60    ///0x28 - prescaler
61    #[inline(always)]
62    pub const fn psc(&self) -> &PSC {
63        &self.psc
64    }
65    ///0x2c - auto-reload register
66    #[inline(always)]
67    pub const fn arr(&self) -> &ARR {
68        &self.arr
69    }
70    ///0x34 - capture/compare register
71    ///
72    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
73    #[inline(always)]
74    pub const fn ccr(&self, n: usize) -> &CCR {
75        &self.ccr[n]
76    }
77    ///Iterator for array of:
78    ///0x34 - capture/compare register
79    #[inline(always)]
80    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
81        self.ccr.iter()
82    }
83    ///0x34 - capture/compare register
84    #[inline(always)]
85    pub const fn ccr1(&self) -> &CCR {
86        self.ccr(0)
87    }
88}
89/**CR1 (rw) register accessor: control register 1
90
91You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
92
93See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:CR1)
94
95For information about available fields see [`mod@cr1`] module*/
96pub type CR1 = crate::Reg<cr1::CR1rs>;
97///control register 1
98pub mod cr1;
99/**DIER (rw) register accessor: DMA/Interrupt enable register
100
101You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
102
103See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:DIER)
104
105For information about available fields see [`mod@dier`] module*/
106pub type DIER = crate::Reg<dier::DIERrs>;
107///DMA/Interrupt enable register
108pub mod dier;
109/**SR (rw) register accessor: status register
110
111You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
112
113See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:SR)
114
115For information about available fields see [`mod@sr`] module*/
116pub type SR = crate::Reg<sr::SRrs>;
117///status register
118pub mod sr;
119/**EGR (w) register accessor: event generation register
120
121You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
122
123See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:EGR)
124
125For information about available fields see [`mod@egr`] module*/
126pub type EGR = crate::Reg<egr::EGRrs>;
127///event generation register
128pub mod egr;
129/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
130
131You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
132
133See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:CCMR1_Output)
134
135For information about available fields see [`mod@ccmr1_output`] module*/
136#[doc(alias = "CCMR1_Output")]
137pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
138///capture/compare mode register (output mode)
139pub mod ccmr1_output;
140/**CCMR1_Input (rw) register accessor: capture/compare mode register (input mode)
141
142You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:CCMR1_Input)
145
146For information about available fields see [`mod@ccmr1_input`] module*/
147#[doc(alias = "CCMR1_Input")]
148pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
149///capture/compare mode register (input mode)
150pub mod ccmr1_input;
151/**CCER (rw) register accessor: capture/compare enable register
152
153You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
154
155See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:CCER)
156
157For information about available fields see [`mod@ccer`] module*/
158pub type CCER = crate::Reg<ccer::CCERrs>;
159///capture/compare enable register
160pub mod ccer;
161/**CNT (rw) register accessor: counter
162
163You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
164
165See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:CNT)
166
167For information about available fields see [`mod@cnt`] module*/
168pub type CNT = crate::Reg<cnt::CNTrs>;
169///counter
170pub mod cnt;
171/**PSC (rw) register accessor: prescaler
172
173You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
174
175See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:PSC)
176
177For information about available fields see [`mod@psc`] module*/
178pub type PSC = crate::Reg<psc::PSCrs>;
179///prescaler
180pub mod psc;
181/**ARR (rw) register accessor: auto-reload register
182
183You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
184
185See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:ARR)
186
187For information about available fields see [`mod@arr`] module*/
188pub type ARR = crate::Reg<arr::ARRrs>;
189///auto-reload register
190pub mod arr;
191/**CCR (rw) register accessor: capture/compare register
192
193You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
194
195See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13:CCR[1])
196
197For information about available fields see [`mod@ccr`] module*/
198pub type CCR = crate::Reg<ccr::CCRrs>;
199///capture/compare register
200pub mod ccr;
stm32f1_staging/stm32f100/tim13.rs

stm32f1_staging/stm32f100/
tim13.rs
