stm32f1_staging/stm32f100/iwdg/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Field `PVU` reader - Watchdog prescaler value update
4pub type PVU_R = crate::BitReader;
5///Field `RVU` reader - Watchdog counter reload value update
6pub type RVU_R = crate::BitReader;
7impl R {
8    ///Bit 0 - Watchdog prescaler value update
9    #[inline(always)]
10    pub fn pvu(&self) -> PVU_R {
11        PVU_R::new((self.bits & 1) != 0)
12    }
13    ///Bit 1 - Watchdog counter reload value update
14    #[inline(always)]
15    pub fn rvu(&self) -> RVU_R {
16        RVU_R::new(((self.bits >> 1) & 1) != 0)
17    }
18}
19impl core::fmt::Debug for R {
20    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21        f.debug_struct("SR").field("pvu", &self.pvu()).field("rvu", &self.rvu()).finish()
22    }
23}
24/**Status register (IWDG_SR)
25
26You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
27
28See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#IWDG:SR)*/
29pub struct SRrs;
30impl crate::RegisterSpec for SRrs {
31    type Ux = u16;
32}
33///`read()` method returns [`sr::R`](R) reader structure
34impl crate::Readable for SRrs {}
35///`reset()` method sets SR to value 0
36impl crate::Resettable for SRrs {}