stm32f1_staging/stm32f100/flash/
acr.rs

1///Register `ACR` reader
2pub type R = crate::R<ACRrs>;
3///Register `ACR` writer
4pub type W = crate::W<ACRrs>;
5///Field `HLFCYA` reader - Flash half cycle access enable
6pub type HLFCYA_R = crate::BitReader;
7///Field `HLFCYA` writer - Flash half cycle access enable
8pub type HLFCYA_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    ///Bit 3 - Flash half cycle access enable
11    #[inline(always)]
12    pub fn hlfcya(&self) -> HLFCYA_R {
13        HLFCYA_R::new(((self.bits >> 3) & 1) != 0)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("ACR").field("hlfcya", &self.hlfcya()).finish()
19    }
20}
21impl W {
22    ///Bit 3 - Flash half cycle access enable
23    #[inline(always)]
24    pub fn hlfcya(&mut self) -> HLFCYA_W<ACRrs> {
25        HLFCYA_W::new(self, 3)
26    }
27}
28/**Flash access control register
29
30You can [`read`](crate::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
31
32See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#FLASH:ACR)*/
33pub struct ACRrs;
34impl crate::RegisterSpec for ACRrs {
35    type Ux = u32;
36}
37///`read()` method returns [`acr::R`](R) reader structure
38impl crate::Readable for ACRrs {}
39///`write(|w| ..)` method takes [`acr::W`](W) writer structure
40impl crate::Writable for ACRrs {
41    type Safety = crate::Unsafe;
42}
43///`reset()` method sets ACR to value 0
44impl crate::Resettable for ACRrs {}
stm32f1_staging/stm32f100/flash/acr.rs

stm32f1_staging/stm32f100/flash/
acr.rs
