stm32f1_staging/stm32f100/dma1/
isr.rs

1///Register `ISR` reader
2pub type R = crate::R<ISRrs>;
3/**Channel %s Global interrupt flag
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum GIF1 {
9    ///0: No transfer error, half event, complete event
10    NoEvent = 0,
11    ///1: A transfer error, half event or complete event has occured
12    Event = 1,
13}
14impl From<GIF1> for bool {
15    #[inline(always)]
16    fn from(variant: GIF1) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `GIF(1-7)` reader - Channel %s Global interrupt flag
21pub type GIF_R = crate::BitReader<GIF1>;
22impl GIF_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> GIF1 {
26        match self.bits {
27            false => GIF1::NoEvent,
28            true => GIF1::Event,
29        }
30    }
31    ///No transfer error, half event, complete event
32    #[inline(always)]
33    pub fn is_no_event(&self) -> bool {
34        *self == GIF1::NoEvent
35    }
36    ///A transfer error, half event or complete event has occured
37    #[inline(always)]
38    pub fn is_event(&self) -> bool {
39        *self == GIF1::Event
40    }
41}
42/**Channel %s Transfer Complete flag
43
44Value on reset: 0*/
45#[cfg_attr(feature = "defmt", derive(defmt::Format))]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum TCIF1 {
48    ///0: No transfer complete event
49    NotComplete = 0,
50    ///1: A transfer complete event has occured
51    Complete = 1,
52}
53impl From<TCIF1> for bool {
54    #[inline(always)]
55    fn from(variant: TCIF1) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `TCIF(1-7)` reader - Channel %s Transfer Complete flag
60pub type TCIF_R = crate::BitReader<TCIF1>;
61impl TCIF_R {
62    ///Get enumerated values variant
63    #[inline(always)]
64    pub const fn variant(&self) -> TCIF1 {
65        match self.bits {
66            false => TCIF1::NotComplete,
67            true => TCIF1::Complete,
68        }
69    }
70    ///No transfer complete event
71    #[inline(always)]
72    pub fn is_not_complete(&self) -> bool {
73        *self == TCIF1::NotComplete
74    }
75    ///A transfer complete event has occured
76    #[inline(always)]
77    pub fn is_complete(&self) -> bool {
78        *self == TCIF1::Complete
79    }
80}
81/**Channel %s Half Transfer Complete flag
82
83Value on reset: 0*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum HTIF1 {
87    ///0: No half transfer event
88    NotHalf = 0,
89    ///1: A half transfer event has occured
90    Half = 1,
91}
92impl From<HTIF1> for bool {
93    #[inline(always)]
94    fn from(variant: HTIF1) -> Self {
95        variant as u8 != 0
96    }
97}
98///Field `HTIF(1-7)` reader - Channel %s Half Transfer Complete flag
99pub type HTIF_R = crate::BitReader<HTIF1>;
100impl HTIF_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub const fn variant(&self) -> HTIF1 {
104        match self.bits {
105            false => HTIF1::NotHalf,
106            true => HTIF1::Half,
107        }
108    }
109    ///No half transfer event
110    #[inline(always)]
111    pub fn is_not_half(&self) -> bool {
112        *self == HTIF1::NotHalf
113    }
114    ///A half transfer event has occured
115    #[inline(always)]
116    pub fn is_half(&self) -> bool {
117        *self == HTIF1::Half
118    }
119}
120/**Channel %s Transfer Error flag
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum TEIF1 {
126    ///0: No transfer error
127    NoError = 0,
128    ///1: A transfer error has occured
129    Error = 1,
130}
131impl From<TEIF1> for bool {
132    #[inline(always)]
133    fn from(variant: TEIF1) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `TEIF(1-7)` reader - Channel %s Transfer Error flag
138pub type TEIF_R = crate::BitReader<TEIF1>;
139impl TEIF_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> TEIF1 {
143        match self.bits {
144            false => TEIF1::NoError,
145            true => TEIF1::Error,
146        }
147    }
148    ///No transfer error
149    #[inline(always)]
150    pub fn is_no_error(&self) -> bool {
151        *self == TEIF1::NoError
152    }
153    ///A transfer error has occured
154    #[inline(always)]
155    pub fn is_error(&self) -> bool {
156        *self == TEIF1::Error
157    }
158}
159impl R {
160    ///Channel (1-7) Global interrupt flag
161    ///
162    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `GIF1` field.</div>
163    #[inline(always)]
164    pub fn gif(&self, n: u8) -> GIF_R {
165        #[allow(clippy::no_effect)] [(); 7][n as usize];
166        GIF_R::new(((self.bits >> (n * 4)) & 1) != 0)
167    }
168    ///Iterator for array of:
169    ///Channel (1-7) Global interrupt flag
170    #[inline(always)]
171    pub fn gif_iter(&self) -> impl Iterator<Item = GIF_R> + '_ {
172        (0..7).map(move |n| GIF_R::new(((self.bits >> (n * 4)) & 1) != 0))
173    }
174    ///Bit 0 - Channel 1 Global interrupt flag
175    #[inline(always)]
176    pub fn gif1(&self) -> GIF_R {
177        GIF_R::new((self.bits & 1) != 0)
178    }
179    ///Bit 4 - Channel 2 Global interrupt flag
180    #[inline(always)]
181    pub fn gif2(&self) -> GIF_R {
182        GIF_R::new(((self.bits >> 4) & 1) != 0)
183    }
184    ///Bit 8 - Channel 3 Global interrupt flag
185    #[inline(always)]
186    pub fn gif3(&self) -> GIF_R {
187        GIF_R::new(((self.bits >> 8) & 1) != 0)
188    }
189    ///Bit 12 - Channel 4 Global interrupt flag
190    #[inline(always)]
191    pub fn gif4(&self) -> GIF_R {
192        GIF_R::new(((self.bits >> 12) & 1) != 0)
193    }
194    ///Bit 16 - Channel 5 Global interrupt flag
195    #[inline(always)]
196    pub fn gif5(&self) -> GIF_R {
197        GIF_R::new(((self.bits >> 16) & 1) != 0)
198    }
199    ///Bit 20 - Channel 6 Global interrupt flag
200    #[inline(always)]
201    pub fn gif6(&self) -> GIF_R {
202        GIF_R::new(((self.bits >> 20) & 1) != 0)
203    }
204    ///Bit 24 - Channel 7 Global interrupt flag
205    #[inline(always)]
206    pub fn gif7(&self) -> GIF_R {
207        GIF_R::new(((self.bits >> 24) & 1) != 0)
208    }
209    ///Channel (1-7) Transfer Complete flag
210    ///
211    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TCIF1` field.</div>
212    #[inline(always)]
213    pub fn tcif(&self, n: u8) -> TCIF_R {
214        #[allow(clippy::no_effect)] [(); 7][n as usize];
215        TCIF_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
216    }
217    ///Iterator for array of:
218    ///Channel (1-7) Transfer Complete flag
219    #[inline(always)]
220    pub fn tcif_iter(&self) -> impl Iterator<Item = TCIF_R> + '_ {
221        (0..7).map(move |n| TCIF_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
222    }
223    ///Bit 1 - Channel 1 Transfer Complete flag
224    #[inline(always)]
225    pub fn tcif1(&self) -> TCIF_R {
226        TCIF_R::new(((self.bits >> 1) & 1) != 0)
227    }
228    ///Bit 5 - Channel 2 Transfer Complete flag
229    #[inline(always)]
230    pub fn tcif2(&self) -> TCIF_R {
231        TCIF_R::new(((self.bits >> 5) & 1) != 0)
232    }
233    ///Bit 9 - Channel 3 Transfer Complete flag
234    #[inline(always)]
235    pub fn tcif3(&self) -> TCIF_R {
236        TCIF_R::new(((self.bits >> 9) & 1) != 0)
237    }
238    ///Bit 13 - Channel 4 Transfer Complete flag
239    #[inline(always)]
240    pub fn tcif4(&self) -> TCIF_R {
241        TCIF_R::new(((self.bits >> 13) & 1) != 0)
242    }
243    ///Bit 17 - Channel 5 Transfer Complete flag
244    #[inline(always)]
245    pub fn tcif5(&self) -> TCIF_R {
246        TCIF_R::new(((self.bits >> 17) & 1) != 0)
247    }
248    ///Bit 21 - Channel 6 Transfer Complete flag
249    #[inline(always)]
250    pub fn tcif6(&self) -> TCIF_R {
251        TCIF_R::new(((self.bits >> 21) & 1) != 0)
252    }
253    ///Bit 25 - Channel 7 Transfer Complete flag
254    #[inline(always)]
255    pub fn tcif7(&self) -> TCIF_R {
256        TCIF_R::new(((self.bits >> 25) & 1) != 0)
257    }
258    ///Channel (1-7) Half Transfer Complete flag
259    ///
260    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `HTIF1` field.</div>
261    #[inline(always)]
262    pub fn htif(&self, n: u8) -> HTIF_R {
263        #[allow(clippy::no_effect)] [(); 7][n as usize];
264        HTIF_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0)
265    }
266    ///Iterator for array of:
267    ///Channel (1-7) Half Transfer Complete flag
268    #[inline(always)]
269    pub fn htif_iter(&self) -> impl Iterator<Item = HTIF_R> + '_ {
270        (0..7).map(move |n| HTIF_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0))
271    }
272    ///Bit 2 - Channel 1 Half Transfer Complete flag
273    #[inline(always)]
274    pub fn htif1(&self) -> HTIF_R {
275        HTIF_R::new(((self.bits >> 2) & 1) != 0)
276    }
277    ///Bit 6 - Channel 2 Half Transfer Complete flag
278    #[inline(always)]
279    pub fn htif2(&self) -> HTIF_R {
280        HTIF_R::new(((self.bits >> 6) & 1) != 0)
281    }
282    ///Bit 10 - Channel 3 Half Transfer Complete flag
283    #[inline(always)]
284    pub fn htif3(&self) -> HTIF_R {
285        HTIF_R::new(((self.bits >> 10) & 1) != 0)
286    }
287    ///Bit 14 - Channel 4 Half Transfer Complete flag
288    #[inline(always)]
289    pub fn htif4(&self) -> HTIF_R {
290        HTIF_R::new(((self.bits >> 14) & 1) != 0)
291    }
292    ///Bit 18 - Channel 5 Half Transfer Complete flag
293    #[inline(always)]
294    pub fn htif5(&self) -> HTIF_R {
295        HTIF_R::new(((self.bits >> 18) & 1) != 0)
296    }
297    ///Bit 22 - Channel 6 Half Transfer Complete flag
298    #[inline(always)]
299    pub fn htif6(&self) -> HTIF_R {
300        HTIF_R::new(((self.bits >> 22) & 1) != 0)
301    }
302    ///Bit 26 - Channel 7 Half Transfer Complete flag
303    #[inline(always)]
304    pub fn htif7(&self) -> HTIF_R {
305        HTIF_R::new(((self.bits >> 26) & 1) != 0)
306    }
307    ///Channel (1-7) Transfer Error flag
308    ///
309    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `TEIF1` field.</div>
310    #[inline(always)]
311    pub fn teif(&self, n: u8) -> TEIF_R {
312        #[allow(clippy::no_effect)] [(); 7][n as usize];
313        TEIF_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0)
314    }
315    ///Iterator for array of:
316    ///Channel (1-7) Transfer Error flag
317    #[inline(always)]
318    pub fn teif_iter(&self) -> impl Iterator<Item = TEIF_R> + '_ {
319        (0..7).map(move |n| TEIF_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0))
320    }
321    ///Bit 3 - Channel 1 Transfer Error flag
322    #[inline(always)]
323    pub fn teif1(&self) -> TEIF_R {
324        TEIF_R::new(((self.bits >> 3) & 1) != 0)
325    }
326    ///Bit 7 - Channel 2 Transfer Error flag
327    #[inline(always)]
328    pub fn teif2(&self) -> TEIF_R {
329        TEIF_R::new(((self.bits >> 7) & 1) != 0)
330    }
331    ///Bit 11 - Channel 3 Transfer Error flag
332    #[inline(always)]
333    pub fn teif3(&self) -> TEIF_R {
334        TEIF_R::new(((self.bits >> 11) & 1) != 0)
335    }
336    ///Bit 15 - Channel 4 Transfer Error flag
337    #[inline(always)]
338    pub fn teif4(&self) -> TEIF_R {
339        TEIF_R::new(((self.bits >> 15) & 1) != 0)
340    }
341    ///Bit 19 - Channel 5 Transfer Error flag
342    #[inline(always)]
343    pub fn teif5(&self) -> TEIF_R {
344        TEIF_R::new(((self.bits >> 19) & 1) != 0)
345    }
346    ///Bit 23 - Channel 6 Transfer Error flag
347    #[inline(always)]
348    pub fn teif6(&self) -> TEIF_R {
349        TEIF_R::new(((self.bits >> 23) & 1) != 0)
350    }
351    ///Bit 27 - Channel 7 Transfer Error flag
352    #[inline(always)]
353    pub fn teif7(&self) -> TEIF_R {
354        TEIF_R::new(((self.bits >> 27) & 1) != 0)
355    }
356}
357impl core::fmt::Debug for R {
358    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
359        f.debug_struct("ISR")
360            .field("gif1", &self.gif1())
361            .field("gif2", &self.gif2())
362            .field("gif3", &self.gif3())
363            .field("gif4", &self.gif4())
364            .field("gif5", &self.gif5())
365            .field("gif6", &self.gif6())
366            .field("gif7", &self.gif7())
367            .field("tcif1", &self.tcif1())
368            .field("tcif2", &self.tcif2())
369            .field("tcif3", &self.tcif3())
370            .field("tcif4", &self.tcif4())
371            .field("tcif5", &self.tcif5())
372            .field("tcif6", &self.tcif6())
373            .field("tcif7", &self.tcif7())
374            .field("htif1", &self.htif1())
375            .field("htif2", &self.htif2())
376            .field("htif3", &self.htif3())
377            .field("htif4", &self.htif4())
378            .field("htif5", &self.htif5())
379            .field("htif6", &self.htif6())
380            .field("htif7", &self.htif7())
381            .field("teif1", &self.teif1())
382            .field("teif2", &self.teif2())
383            .field("teif3", &self.teif3())
384            .field("teif4", &self.teif4())
385            .field("teif5", &self.teif5())
386            .field("teif6", &self.teif6())
387            .field("teif7", &self.teif7())
388            .finish()
389    }
390}
391/**DMA interrupt status register (DMA_ISR)
392
393You can [`read`](crate::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
394
395See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DMA1:ISR)*/
396pub struct ISRrs;
397impl crate::RegisterSpec for ISRrs {
398    type Ux = u32;
399}
400///`read()` method returns [`isr::R`](R) reader structure
401impl crate::Readable for ISRrs {}
402///`reset()` method sets ISR to value 0
403impl crate::Resettable for ISRrs {}
stm32f1_staging/stm32f100/dma1/isr.rs

stm32f1_staging/stm32f100/dma1/
isr.rs
