stm32f1_staging/stm32f100/dac/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**DAC channel1 enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EN1 {
11    ///0: DAC channel X disabled
12    Disabled = 0,
13    ///1: DAC channel X enabled
14    Enabled = 1,
15}
16impl From<EN1> for bool {
17    #[inline(always)]
18    fn from(variant: EN1) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EN1` reader - DAC channel1 enable
23pub type EN1_R = crate::BitReader<EN1>;
24impl EN1_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EN1 {
28        match self.bits {
29            false => EN1::Disabled,
30            true => EN1::Enabled,
31        }
32    }
33    ///DAC channel X disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EN1::Disabled
37    }
38    ///DAC channel X enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EN1::Enabled
42    }
43}
44///Field `EN1` writer - DAC channel1 enable
45pub type EN1_W<'a, REG> = crate::BitWriter<'a, REG, EN1>;
46impl<'a, REG> EN1_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///DAC channel X disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EN1::Disabled)
54    }
55    ///DAC channel X enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EN1::Enabled)
59    }
60}
61/**DAC channel1 output buffer disable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum BOFF1 {
67    ///0: DAC channel X output buffer enabled
68    Enabled = 0,
69    ///1: DAC channel X output buffer disabled
70    Disabled = 1,
71}
72impl From<BOFF1> for bool {
73    #[inline(always)]
74    fn from(variant: BOFF1) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `BOFF1` reader - DAC channel1 output buffer disable
79pub type BOFF1_R = crate::BitReader<BOFF1>;
80impl BOFF1_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> BOFF1 {
84        match self.bits {
85            false => BOFF1::Enabled,
86            true => BOFF1::Disabled,
87        }
88    }
89    ///DAC channel X output buffer enabled
90    #[inline(always)]
91    pub fn is_enabled(&self) -> bool {
92        *self == BOFF1::Enabled
93    }
94    ///DAC channel X output buffer disabled
95    #[inline(always)]
96    pub fn is_disabled(&self) -> bool {
97        *self == BOFF1::Disabled
98    }
99}
100///Field `BOFF1` writer - DAC channel1 output buffer disable
101pub type BOFF1_W<'a, REG> = crate::BitWriter<'a, REG, BOFF1>;
102impl<'a, REG> BOFF1_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///DAC channel X output buffer enabled
107    #[inline(always)]
108    pub fn enabled(self) -> &'a mut crate::W<REG> {
109        self.variant(BOFF1::Enabled)
110    }
111    ///DAC channel X output buffer disabled
112    #[inline(always)]
113    pub fn disabled(self) -> &'a mut crate::W<REG> {
114        self.variant(BOFF1::Disabled)
115    }
116}
117/**DAC channel1 trigger enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum TEN1 {
123    ///0: DAC channel X trigger disabled
124    Disabled = 0,
125    ///1: DAC channel X trigger enabled
126    Enabled = 1,
127}
128impl From<TEN1> for bool {
129    #[inline(always)]
130    fn from(variant: TEN1) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `TEN1` reader - DAC channel1 trigger enable
135pub type TEN1_R = crate::BitReader<TEN1>;
136impl TEN1_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> TEN1 {
140        match self.bits {
141            false => TEN1::Disabled,
142            true => TEN1::Enabled,
143        }
144    }
145    ///DAC channel X trigger disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == TEN1::Disabled
149    }
150    ///DAC channel X trigger enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == TEN1::Enabled
154    }
155}
156///Field `TEN1` writer - DAC channel1 trigger enable
157pub type TEN1_W<'a, REG> = crate::BitWriter<'a, REG, TEN1>;
158impl<'a, REG> TEN1_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///DAC channel X trigger disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(TEN1::Disabled)
166    }
167    ///DAC channel X trigger enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(TEN1::Enabled)
171    }
172}
173/**DAC channel1 trigger selection
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178#[repr(u8)]
179pub enum TSEL1 {
180    ///0: Timer 6 TRGO event
181    Tim6Trgo = 0,
182    ///1: Timer 3 TRGO event
183    Tim3Trgo = 1,
184    ///2: Timer 7 TRGO event
185    Tim7Trgo = 2,
186    ///3: Timer 15 TRGO event
187    Tim15Trgo = 3,
188    ///4: Timer 2 TRGO event
189    Tim2Trgo = 4,
190    ///6: EXTI line9
191    Exti9 = 6,
192    ///7: Software trigger
193    Software = 7,
194}
195impl From<TSEL1> for u8 {
196    #[inline(always)]
197    fn from(variant: TSEL1) -> Self {
198        variant as _
199    }
200}
201impl crate::FieldSpec for TSEL1 {
202    type Ux = u8;
203}
204impl crate::IsEnum for TSEL1 {}
205///Field `TSEL1` reader - DAC channel1 trigger selection
206pub type TSEL1_R = crate::FieldReader<TSEL1>;
207impl TSEL1_R {
208    ///Get enumerated values variant
209    #[inline(always)]
210    pub const fn variant(&self) -> Option<TSEL1> {
211        match self.bits {
212            0 => Some(TSEL1::Tim6Trgo),
213            1 => Some(TSEL1::Tim3Trgo),
214            2 => Some(TSEL1::Tim7Trgo),
215            3 => Some(TSEL1::Tim15Trgo),
216            4 => Some(TSEL1::Tim2Trgo),
217            6 => Some(TSEL1::Exti9),
218            7 => Some(TSEL1::Software),
219            _ => None,
220        }
221    }
222    ///Timer 6 TRGO event
223    #[inline(always)]
224    pub fn is_tim6_trgo(&self) -> bool {
225        *self == TSEL1::Tim6Trgo
226    }
227    ///Timer 3 TRGO event
228    #[inline(always)]
229    pub fn is_tim3_trgo(&self) -> bool {
230        *self == TSEL1::Tim3Trgo
231    }
232    ///Timer 7 TRGO event
233    #[inline(always)]
234    pub fn is_tim7_trgo(&self) -> bool {
235        *self == TSEL1::Tim7Trgo
236    }
237    ///Timer 15 TRGO event
238    #[inline(always)]
239    pub fn is_tim15_trgo(&self) -> bool {
240        *self == TSEL1::Tim15Trgo
241    }
242    ///Timer 2 TRGO event
243    #[inline(always)]
244    pub fn is_tim2_trgo(&self) -> bool {
245        *self == TSEL1::Tim2Trgo
246    }
247    ///EXTI line9
248    #[inline(always)]
249    pub fn is_exti9(&self) -> bool {
250        *self == TSEL1::Exti9
251    }
252    ///Software trigger
253    #[inline(always)]
254    pub fn is_software(&self) -> bool {
255        *self == TSEL1::Software
256    }
257}
258///Field `TSEL1` writer - DAC channel1 trigger selection
259pub type TSEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TSEL1>;
260impl<'a, REG> TSEL1_W<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263    REG::Ux: From<u8>,
264{
265    ///Timer 6 TRGO event
266    #[inline(always)]
267    pub fn tim6_trgo(self) -> &'a mut crate::W<REG> {
268        self.variant(TSEL1::Tim6Trgo)
269    }
270    ///Timer 3 TRGO event
271    #[inline(always)]
272    pub fn tim3_trgo(self) -> &'a mut crate::W<REG> {
273        self.variant(TSEL1::Tim3Trgo)
274    }
275    ///Timer 7 TRGO event
276    #[inline(always)]
277    pub fn tim7_trgo(self) -> &'a mut crate::W<REG> {
278        self.variant(TSEL1::Tim7Trgo)
279    }
280    ///Timer 15 TRGO event
281    #[inline(always)]
282    pub fn tim15_trgo(self) -> &'a mut crate::W<REG> {
283        self.variant(TSEL1::Tim15Trgo)
284    }
285    ///Timer 2 TRGO event
286    #[inline(always)]
287    pub fn tim2_trgo(self) -> &'a mut crate::W<REG> {
288        self.variant(TSEL1::Tim2Trgo)
289    }
290    ///EXTI line9
291    #[inline(always)]
292    pub fn exti9(self) -> &'a mut crate::W<REG> {
293        self.variant(TSEL1::Exti9)
294    }
295    ///Software trigger
296    #[inline(always)]
297    pub fn software(self) -> &'a mut crate::W<REG> {
298        self.variant(TSEL1::Software)
299    }
300}
301/**DAC channel1 noise/triangle wave generation enable
302
303Value on reset: 0*/
304#[cfg_attr(feature = "defmt", derive(defmt::Format))]
305#[derive(Clone, Copy, Debug, PartialEq, Eq)]
306#[repr(u8)]
307pub enum WAVE1 {
308    ///0: Wave generation disabled
309    Disabled = 0,
310    ///1: Noise wave generation enabled
311    Noise = 1,
312    ///2: Triangle wave generation enabled
313    Triangle = 2,
314}
315impl From<WAVE1> for u8 {
316    #[inline(always)]
317    fn from(variant: WAVE1) -> Self {
318        variant as _
319    }
320}
321impl crate::FieldSpec for WAVE1 {
322    type Ux = u8;
323}
324impl crate::IsEnum for WAVE1 {}
325///Field `WAVE1` reader - DAC channel1 noise/triangle wave generation enable
326pub type WAVE1_R = crate::FieldReader<WAVE1>;
327impl WAVE1_R {
328    ///Get enumerated values variant
329    #[inline(always)]
330    pub const fn variant(&self) -> Option<WAVE1> {
331        match self.bits {
332            0 => Some(WAVE1::Disabled),
333            1 => Some(WAVE1::Noise),
334            2 => Some(WAVE1::Triangle),
335            _ => None,
336        }
337    }
338    ///Wave generation disabled
339    #[inline(always)]
340    pub fn is_disabled(&self) -> bool {
341        *self == WAVE1::Disabled
342    }
343    ///Noise wave generation enabled
344    #[inline(always)]
345    pub fn is_noise(&self) -> bool {
346        *self == WAVE1::Noise
347    }
348    ///Triangle wave generation enabled
349    #[inline(always)]
350    pub fn is_triangle(&self) -> bool {
351        *self == WAVE1::Triangle
352    }
353}
354///Field `WAVE1` writer - DAC channel1 noise/triangle wave generation enable
355pub type WAVE1_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WAVE1>;
356impl<'a, REG> WAVE1_W<'a, REG>
357where
358    REG: crate::Writable + crate::RegisterSpec,
359    REG::Ux: From<u8>,
360{
361    ///Wave generation disabled
362    #[inline(always)]
363    pub fn disabled(self) -> &'a mut crate::W<REG> {
364        self.variant(WAVE1::Disabled)
365    }
366    ///Noise wave generation enabled
367    #[inline(always)]
368    pub fn noise(self) -> &'a mut crate::W<REG> {
369        self.variant(WAVE1::Noise)
370    }
371    ///Triangle wave generation enabled
372    #[inline(always)]
373    pub fn triangle(self) -> &'a mut crate::W<REG> {
374        self.variant(WAVE1::Triangle)
375    }
376}
377///Field `MAMP1` reader - DAC channel1 mask/amplitude selector
378pub type MAMP1_R = crate::FieldReader;
379///Field `MAMP1` writer - DAC channel1 mask/amplitude selector
380pub type MAMP1_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
381/**DAC channel1 DMA enable
382
383Value on reset: 0*/
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum DMAEN1 {
387    ///0: DAC channel X DMA mode disabled
388    Disabled = 0,
389    ///1: DAC channel X DMA mode enabled
390    Enabled = 1,
391}
392impl From<DMAEN1> for bool {
393    #[inline(always)]
394    fn from(variant: DMAEN1) -> Self {
395        variant as u8 != 0
396    }
397}
398///Field `DMAEN1` reader - DAC channel1 DMA enable
399pub type DMAEN1_R = crate::BitReader<DMAEN1>;
400impl DMAEN1_R {
401    ///Get enumerated values variant
402    #[inline(always)]
403    pub const fn variant(&self) -> DMAEN1 {
404        match self.bits {
405            false => DMAEN1::Disabled,
406            true => DMAEN1::Enabled,
407        }
408    }
409    ///DAC channel X DMA mode disabled
410    #[inline(always)]
411    pub fn is_disabled(&self) -> bool {
412        *self == DMAEN1::Disabled
413    }
414    ///DAC channel X DMA mode enabled
415    #[inline(always)]
416    pub fn is_enabled(&self) -> bool {
417        *self == DMAEN1::Enabled
418    }
419}
420///Field `DMAEN1` writer - DAC channel1 DMA enable
421pub type DMAEN1_W<'a, REG> = crate::BitWriter<'a, REG, DMAEN1>;
422impl<'a, REG> DMAEN1_W<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    ///DAC channel X DMA mode disabled
427    #[inline(always)]
428    pub fn disabled(self) -> &'a mut crate::W<REG> {
429        self.variant(DMAEN1::Disabled)
430    }
431    ///DAC channel X DMA mode enabled
432    #[inline(always)]
433    pub fn enabled(self) -> &'a mut crate::W<REG> {
434        self.variant(DMAEN1::Enabled)
435    }
436}
437/**DAC channel1 DMA underrun interrupt enable
438
439Value on reset: 0*/
440#[cfg_attr(feature = "defmt", derive(defmt::Format))]
441#[derive(Clone, Copy, Debug, PartialEq, Eq)]
442pub enum DMAUDRIE1 {
443    ///0: DAC channel X DMA Underrun Interrupt disabled
444    Disabled = 0,
445    ///1: DAC channel X DMA Underrun Interrupt enabled
446    Enabled = 1,
447}
448impl From<DMAUDRIE1> for bool {
449    #[inline(always)]
450    fn from(variant: DMAUDRIE1) -> Self {
451        variant as u8 != 0
452    }
453}
454///Field `DMAUDRIE1` reader - DAC channel1 DMA underrun interrupt enable
455pub type DMAUDRIE1_R = crate::BitReader<DMAUDRIE1>;
456impl DMAUDRIE1_R {
457    ///Get enumerated values variant
458    #[inline(always)]
459    pub const fn variant(&self) -> DMAUDRIE1 {
460        match self.bits {
461            false => DMAUDRIE1::Disabled,
462            true => DMAUDRIE1::Enabled,
463        }
464    }
465    ///DAC channel X DMA Underrun Interrupt disabled
466    #[inline(always)]
467    pub fn is_disabled(&self) -> bool {
468        *self == DMAUDRIE1::Disabled
469    }
470    ///DAC channel X DMA Underrun Interrupt enabled
471    #[inline(always)]
472    pub fn is_enabled(&self) -> bool {
473        *self == DMAUDRIE1::Enabled
474    }
475}
476///Field `DMAUDRIE1` writer - DAC channel1 DMA underrun interrupt enable
477pub type DMAUDRIE1_W<'a, REG> = crate::BitWriter<'a, REG, DMAUDRIE1>;
478impl<'a, REG> DMAUDRIE1_W<'a, REG>
479where
480    REG: crate::Writable + crate::RegisterSpec,
481{
482    ///DAC channel X DMA Underrun Interrupt disabled
483    #[inline(always)]
484    pub fn disabled(self) -> &'a mut crate::W<REG> {
485        self.variant(DMAUDRIE1::Disabled)
486    }
487    ///DAC channel X DMA Underrun Interrupt enabled
488    #[inline(always)]
489    pub fn enabled(self) -> &'a mut crate::W<REG> {
490        self.variant(DMAUDRIE1::Enabled)
491    }
492}
493///Field `BOFF2` reader - DAC channel2 output buffer disable
494pub use BOFF1_R as BOFF2_R;
495///Field `BOFF2` writer - DAC channel2 output buffer disable
496pub use BOFF1_W as BOFF2_W;
497///Field `EN2` reader - DAC channel2 enable
498pub use EN1_R as EN2_R;
499///Field `EN2` writer - DAC channel2 enable
500pub use EN1_W as EN2_W;
501///Field `TEN2` reader - DAC channel2 trigger enable
502pub use TEN1_R as TEN2_R;
503///Field `TEN2` writer - DAC channel2 trigger enable
504pub use TEN1_W as TEN2_W;
505/**DAC channel2 trigger selection
506
507Value on reset: 0*/
508#[cfg_attr(feature = "defmt", derive(defmt::Format))]
509#[derive(Clone, Copy, Debug, PartialEq, Eq)]
510#[repr(u8)]
511pub enum TSEL2 {
512    ///0: Timer 6 TRGO event
513    Tim6Trgo = 0,
514    ///1: Timer 8 TRGO event
515    Tim8Trgo = 1,
516    ///2: Timer 7 TRGO event
517    Tim7Trgo = 2,
518    ///3: Timer 5 TRGO event
519    Tim5Trgo = 3,
520    ///4: Timer 2 TRGO event
521    Tim2Trgo = 4,
522    ///5: Timer 4 TRGO event
523    Tim4Trgo = 5,
524    ///6: EXTI line9
525    Exti9 = 6,
526    ///7: Software trigger
527    Software = 7,
528}
529impl From<TSEL2> for u8 {
530    #[inline(always)]
531    fn from(variant: TSEL2) -> Self {
532        variant as _
533    }
534}
535impl crate::FieldSpec for TSEL2 {
536    type Ux = u8;
537}
538impl crate::IsEnum for TSEL2 {}
539///Field `TSEL2` reader - DAC channel2 trigger selection
540pub type TSEL2_R = crate::FieldReader<TSEL2>;
541impl TSEL2_R {
542    ///Get enumerated values variant
543    #[inline(always)]
544    pub const fn variant(&self) -> TSEL2 {
545        match self.bits {
546            0 => TSEL2::Tim6Trgo,
547            1 => TSEL2::Tim8Trgo,
548            2 => TSEL2::Tim7Trgo,
549            3 => TSEL2::Tim5Trgo,
550            4 => TSEL2::Tim2Trgo,
551            5 => TSEL2::Tim4Trgo,
552            6 => TSEL2::Exti9,
553            7 => TSEL2::Software,
554            _ => unreachable!(),
555        }
556    }
557    ///Timer 6 TRGO event
558    #[inline(always)]
559    pub fn is_tim6_trgo(&self) -> bool {
560        *self == TSEL2::Tim6Trgo
561    }
562    ///Timer 8 TRGO event
563    #[inline(always)]
564    pub fn is_tim8_trgo(&self) -> bool {
565        *self == TSEL2::Tim8Trgo
566    }
567    ///Timer 7 TRGO event
568    #[inline(always)]
569    pub fn is_tim7_trgo(&self) -> bool {
570        *self == TSEL2::Tim7Trgo
571    }
572    ///Timer 5 TRGO event
573    #[inline(always)]
574    pub fn is_tim5_trgo(&self) -> bool {
575        *self == TSEL2::Tim5Trgo
576    }
577    ///Timer 2 TRGO event
578    #[inline(always)]
579    pub fn is_tim2_trgo(&self) -> bool {
580        *self == TSEL2::Tim2Trgo
581    }
582    ///Timer 4 TRGO event
583    #[inline(always)]
584    pub fn is_tim4_trgo(&self) -> bool {
585        *self == TSEL2::Tim4Trgo
586    }
587    ///EXTI line9
588    #[inline(always)]
589    pub fn is_exti9(&self) -> bool {
590        *self == TSEL2::Exti9
591    }
592    ///Software trigger
593    #[inline(always)]
594    pub fn is_software(&self) -> bool {
595        *self == TSEL2::Software
596    }
597}
598///Field `TSEL2` writer - DAC channel2 trigger selection
599pub type TSEL2_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TSEL2, crate::Safe>;
600impl<'a, REG> TSEL2_W<'a, REG>
601where
602    REG: crate::Writable + crate::RegisterSpec,
603    REG::Ux: From<u8>,
604{
605    ///Timer 6 TRGO event
606    #[inline(always)]
607    pub fn tim6_trgo(self) -> &'a mut crate::W<REG> {
608        self.variant(TSEL2::Tim6Trgo)
609    }
610    ///Timer 8 TRGO event
611    #[inline(always)]
612    pub fn tim8_trgo(self) -> &'a mut crate::W<REG> {
613        self.variant(TSEL2::Tim8Trgo)
614    }
615    ///Timer 7 TRGO event
616    #[inline(always)]
617    pub fn tim7_trgo(self) -> &'a mut crate::W<REG> {
618        self.variant(TSEL2::Tim7Trgo)
619    }
620    ///Timer 5 TRGO event
621    #[inline(always)]
622    pub fn tim5_trgo(self) -> &'a mut crate::W<REG> {
623        self.variant(TSEL2::Tim5Trgo)
624    }
625    ///Timer 2 TRGO event
626    #[inline(always)]
627    pub fn tim2_trgo(self) -> &'a mut crate::W<REG> {
628        self.variant(TSEL2::Tim2Trgo)
629    }
630    ///Timer 4 TRGO event
631    #[inline(always)]
632    pub fn tim4_trgo(self) -> &'a mut crate::W<REG> {
633        self.variant(TSEL2::Tim4Trgo)
634    }
635    ///EXTI line9
636    #[inline(always)]
637    pub fn exti9(self) -> &'a mut crate::W<REG> {
638        self.variant(TSEL2::Exti9)
639    }
640    ///Software trigger
641    #[inline(always)]
642    pub fn software(self) -> &'a mut crate::W<REG> {
643        self.variant(TSEL2::Software)
644    }
645}
646///Field `WAVE2` reader - DAC channel2 noise/triangle wave generation enable
647pub use WAVE1_R as WAVE2_R;
648///Field `WAVE2` writer - DAC channel2 noise/triangle wave generation enable
649pub use WAVE1_W as WAVE2_W;
650///Field `MAMP2` reader - DAC channel2 mask/amplitude selector
651pub type MAMP2_R = crate::FieldReader;
652///Field `MAMP2` writer - DAC channel2 mask/amplitude selector
653pub type MAMP2_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
654///Field `DMAEN2` reader - DAC channel2 DMA enable
655pub use DMAEN1_R as DMAEN2_R;
656///Field `DMAEN2` writer - DAC channel2 DMA enable
657pub use DMAEN1_W as DMAEN2_W;
658///Field `DMAUDRIE2` reader - DAC channel2 DMA underrun interrupt enable
659pub use DMAUDRIE1_R as DMAUDRIE2_R;
660///Field `DMAUDRIE2` writer - DAC channel2 DMA underrun interrupt enable
661pub use DMAUDRIE1_W as DMAUDRIE2_W;
662impl R {
663    ///Bit 0 - DAC channel1 enable
664    #[inline(always)]
665    pub fn en1(&self) -> EN1_R {
666        EN1_R::new((self.bits & 1) != 0)
667    }
668    ///Bit 1 - DAC channel1 output buffer disable
669    #[inline(always)]
670    pub fn boff1(&self) -> BOFF1_R {
671        BOFF1_R::new(((self.bits >> 1) & 1) != 0)
672    }
673    ///Bit 2 - DAC channel1 trigger enable
674    #[inline(always)]
675    pub fn ten1(&self) -> TEN1_R {
676        TEN1_R::new(((self.bits >> 2) & 1) != 0)
677    }
678    ///Bits 3:5 - DAC channel1 trigger selection
679    #[inline(always)]
680    pub fn tsel1(&self) -> TSEL1_R {
681        TSEL1_R::new(((self.bits >> 3) & 7) as u8)
682    }
683    ///Bits 6:7 - DAC channel1 noise/triangle wave generation enable
684    #[inline(always)]
685    pub fn wave1(&self) -> WAVE1_R {
686        WAVE1_R::new(((self.bits >> 6) & 3) as u8)
687    }
688    ///Bits 8:11 - DAC channel1 mask/amplitude selector
689    #[inline(always)]
690    pub fn mamp1(&self) -> MAMP1_R {
691        MAMP1_R::new(((self.bits >> 8) & 0x0f) as u8)
692    }
693    ///Bit 12 - DAC channel1 DMA enable
694    #[inline(always)]
695    pub fn dmaen1(&self) -> DMAEN1_R {
696        DMAEN1_R::new(((self.bits >> 12) & 1) != 0)
697    }
698    ///Bit 13 - DAC channel1 DMA underrun interrupt enable
699    #[inline(always)]
700    pub fn dmaudrie1(&self) -> DMAUDRIE1_R {
701        DMAUDRIE1_R::new(((self.bits >> 13) & 1) != 0)
702    }
703    ///Bit 16 - DAC channel2 enable
704    #[inline(always)]
705    pub fn en2(&self) -> EN2_R {
706        EN2_R::new(((self.bits >> 16) & 1) != 0)
707    }
708    ///Bit 17 - DAC channel2 output buffer disable
709    #[inline(always)]
710    pub fn boff2(&self) -> BOFF2_R {
711        BOFF2_R::new(((self.bits >> 17) & 1) != 0)
712    }
713    ///Bit 18 - DAC channel2 trigger enable
714    #[inline(always)]
715    pub fn ten2(&self) -> TEN2_R {
716        TEN2_R::new(((self.bits >> 18) & 1) != 0)
717    }
718    ///Bits 19:21 - DAC channel2 trigger selection
719    #[inline(always)]
720    pub fn tsel2(&self) -> TSEL2_R {
721        TSEL2_R::new(((self.bits >> 19) & 7) as u8)
722    }
723    ///Bits 22:23 - DAC channel2 noise/triangle wave generation enable
724    #[inline(always)]
725    pub fn wave2(&self) -> WAVE2_R {
726        WAVE2_R::new(((self.bits >> 22) & 3) as u8)
727    }
728    ///Bits 24:27 - DAC channel2 mask/amplitude selector
729    #[inline(always)]
730    pub fn mamp2(&self) -> MAMP2_R {
731        MAMP2_R::new(((self.bits >> 24) & 0x0f) as u8)
732    }
733    ///Bit 28 - DAC channel2 DMA enable
734    #[inline(always)]
735    pub fn dmaen2(&self) -> DMAEN2_R {
736        DMAEN2_R::new(((self.bits >> 28) & 1) != 0)
737    }
738    ///Bit 29 - DAC channel2 DMA underrun interrupt enable
739    #[inline(always)]
740    pub fn dmaudrie2(&self) -> DMAUDRIE2_R {
741        DMAUDRIE2_R::new(((self.bits >> 29) & 1) != 0)
742    }
743}
744impl core::fmt::Debug for R {
745    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
746        f.debug_struct("CR")
747            .field("en1", &self.en1())
748            .field("boff1", &self.boff1())
749            .field("ten1", &self.ten1())
750            .field("tsel1", &self.tsel1())
751            .field("wave1", &self.wave1())
752            .field("mamp1", &self.mamp1())
753            .field("dmaen1", &self.dmaen1())
754            .field("en2", &self.en2())
755            .field("boff2", &self.boff2())
756            .field("ten2", &self.ten2())
757            .field("tsel2", &self.tsel2())
758            .field("wave2", &self.wave2())
759            .field("mamp2", &self.mamp2())
760            .field("dmaen2", &self.dmaen2())
761            .field("dmaudrie1", &self.dmaudrie1())
762            .field("dmaudrie2", &self.dmaudrie2())
763            .finish()
764    }
765}
766impl W {
767    ///Bit 0 - DAC channel1 enable
768    #[inline(always)]
769    pub fn en1(&mut self) -> EN1_W<CRrs> {
770        EN1_W::new(self, 0)
771    }
772    ///Bit 1 - DAC channel1 output buffer disable
773    #[inline(always)]
774    pub fn boff1(&mut self) -> BOFF1_W<CRrs> {
775        BOFF1_W::new(self, 1)
776    }
777    ///Bit 2 - DAC channel1 trigger enable
778    #[inline(always)]
779    pub fn ten1(&mut self) -> TEN1_W<CRrs> {
780        TEN1_W::new(self, 2)
781    }
782    ///Bits 3:5 - DAC channel1 trigger selection
783    #[inline(always)]
784    pub fn tsel1(&mut self) -> TSEL1_W<CRrs> {
785        TSEL1_W::new(self, 3)
786    }
787    ///Bits 6:7 - DAC channel1 noise/triangle wave generation enable
788    #[inline(always)]
789    pub fn wave1(&mut self) -> WAVE1_W<CRrs> {
790        WAVE1_W::new(self, 6)
791    }
792    ///Bits 8:11 - DAC channel1 mask/amplitude selector
793    #[inline(always)]
794    pub fn mamp1(&mut self) -> MAMP1_W<CRrs> {
795        MAMP1_W::new(self, 8)
796    }
797    ///Bit 12 - DAC channel1 DMA enable
798    #[inline(always)]
799    pub fn dmaen1(&mut self) -> DMAEN1_W<CRrs> {
800        DMAEN1_W::new(self, 12)
801    }
802    ///Bit 13 - DAC channel1 DMA underrun interrupt enable
803    #[inline(always)]
804    pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<CRrs> {
805        DMAUDRIE1_W::new(self, 13)
806    }
807    ///Bit 16 - DAC channel2 enable
808    #[inline(always)]
809    pub fn en2(&mut self) -> EN2_W<CRrs> {
810        EN2_W::new(self, 16)
811    }
812    ///Bit 17 - DAC channel2 output buffer disable
813    #[inline(always)]
814    pub fn boff2(&mut self) -> BOFF2_W<CRrs> {
815        BOFF2_W::new(self, 17)
816    }
817    ///Bit 18 - DAC channel2 trigger enable
818    #[inline(always)]
819    pub fn ten2(&mut self) -> TEN2_W<CRrs> {
820        TEN2_W::new(self, 18)
821    }
822    ///Bits 19:21 - DAC channel2 trigger selection
823    #[inline(always)]
824    pub fn tsel2(&mut self) -> TSEL2_W<CRrs> {
825        TSEL2_W::new(self, 19)
826    }
827    ///Bits 22:23 - DAC channel2 noise/triangle wave generation enable
828    #[inline(always)]
829    pub fn wave2(&mut self) -> WAVE2_W<CRrs> {
830        WAVE2_W::new(self, 22)
831    }
832    ///Bits 24:27 - DAC channel2 mask/amplitude selector
833    #[inline(always)]
834    pub fn mamp2(&mut self) -> MAMP2_W<CRrs> {
835        MAMP2_W::new(self, 24)
836    }
837    ///Bit 28 - DAC channel2 DMA enable
838    #[inline(always)]
839    pub fn dmaen2(&mut self) -> DMAEN2_W<CRrs> {
840        DMAEN2_W::new(self, 28)
841    }
842    ///Bit 29 - DAC channel2 DMA underrun interrupt enable
843    #[inline(always)]
844    pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<CRrs> {
845        DMAUDRIE2_W::new(self, 29)
846    }
847}
848/**Control register (DAC_CR)
849
850You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
851
852See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC:CR)*/
853pub struct CRrs;
854impl crate::RegisterSpec for CRrs {
855    type Ux = u32;
856}
857///`read()` method returns [`cr::R`](R) reader structure
858impl crate::Readable for CRrs {}
859///`write(|w| ..)` method takes [`cr::W`](W) writer structure
860impl crate::Writable for CRrs {
861    type Safety = crate::Unsafe;
862}
863///`reset()` method sets CR to value 0
864impl crate::Resettable for CRrs {}
stm32f1_staging/stm32f100/dac/cr.rs

stm32f1_staging/stm32f100/dac/
cr.rs
