stm32f1_staging/stm32f107/
usart1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    sr: SR,
6    _reserved1: [u8; 0x02],
7    dr: DR,
8    _reserved2: [u8; 0x02],
9    brr: BRR,
10    _reserved3: [u8; 0x02],
11    cr1: CR1,
12    _reserved4: [u8; 0x02],
13    cr2: CR2,
14    _reserved5: [u8; 0x02],
15    cr3: CR3,
16    _reserved6: [u8; 0x02],
17    gtpr: GTPR,
18}
19impl RegisterBlock {
20    ///0x00 - Status register
21    #[inline(always)]
22    pub const fn sr(&self) -> &SR {
23        &self.sr
24    }
25    ///0x04 - Data register
26    #[inline(always)]
27    pub const fn dr(&self) -> &DR {
28        &self.dr
29    }
30    ///0x08 - Baud rate register
31    #[inline(always)]
32    pub const fn brr(&self) -> &BRR {
33        &self.brr
34    }
35    ///0x0c - Control register 1
36    #[inline(always)]
37    pub const fn cr1(&self) -> &CR1 {
38        &self.cr1
39    }
40    ///0x10 - Control register 2
41    #[inline(always)]
42    pub const fn cr2(&self) -> &CR2 {
43        &self.cr2
44    }
45    ///0x14 - Control register 3
46    #[inline(always)]
47    pub const fn cr3(&self) -> &CR3 {
48        &self.cr3
49    }
50    ///0x18 - Guard time and prescaler register
51    #[inline(always)]
52    pub const fn gtpr(&self) -> &GTPR {
53        &self.gtpr
54    }
55}
56/**SR (rw) register accessor: Status register
57
58You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
59
60See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1:SR)
61
62For information about available fields see [`mod@sr`] module*/
63pub type SR = crate::Reg<sr::SRrs>;
64///Status register
65pub mod sr;
66/**DR (rw) register accessor: Data register
67
68You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
69
70See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1:DR)
71
72For information about available fields see [`mod@dr`] module*/
73pub type DR = crate::Reg<dr::DRrs>;
74///Data register
75pub mod dr;
76/**BRR (rw) register accessor: Baud rate register
77
78You can [`read`](crate::Reg::read) this register and get [`brr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
79
80See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1:BRR)
81
82For information about available fields see [`mod@brr`] module*/
83pub type BRR = crate::Reg<brr::BRRrs>;
84///Baud rate register
85pub mod brr;
86/**CR1 (rw) register accessor: Control register 1
87
88You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
89
90See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1:CR1)
91
92For information about available fields see [`mod@cr1`] module*/
93pub type CR1 = crate::Reg<cr1::CR1rs>;
94///Control register 1
95pub mod cr1;
96/**CR2 (rw) register accessor: Control register 2
97
98You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
99
100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1:CR2)
101
102For information about available fields see [`mod@cr2`] module*/
103pub type CR2 = crate::Reg<cr2::CR2rs>;
104///Control register 2
105pub mod cr2;
106/**CR3 (rw) register accessor: Control register 3
107
108You can [`read`](crate::Reg::read) this register and get [`cr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
109
110See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1:CR3)
111
112For information about available fields see [`mod@cr3`] module*/
113pub type CR3 = crate::Reg<cr3::CR3rs>;
114///Control register 3
115pub mod cr3;
116/**GTPR (rw) register accessor: Guard time and prescaler register
117
118You can [`read`](crate::Reg::read) this register and get [`gtpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gtpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
119
120See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1:GTPR)
121
122For information about available fields see [`mod@gtpr`] module*/
123pub type GTPR = crate::Reg<gtpr::GTPRrs>;
124///Guard time and prescaler register
125pub mod gtpr;
stm32f1_staging/stm32f107/usart1.rs

stm32f1_staging/stm32f107/
usart1.rs
