stm32f1_staging/stm32f107/sdio/
dctrl.rs

1///Register `DCTRL` reader
2pub type R = crate::R<DCTRLrs>;
3///Register `DCTRL` writer
4pub type W = crate::W<DCTRLrs>;
5///Field `DTEN` reader - DTEN
6pub type DTEN_R = crate::BitReader;
7///Field `DTEN` writer - DTEN
8pub type DTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DTDIR` reader - Data transfer direction selection
10pub type DTDIR_R = crate::BitReader;
11///Field `DTDIR` writer - Data transfer direction selection
12pub type DTDIR_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DTMODE` reader - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
14pub type DTMODE_R = crate::BitReader;
15///Field `DTMODE` writer - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
16pub type DTMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `DMAEN` reader - DMA enable bit
18pub type DMAEN_R = crate::BitReader;
19///Field `DMAEN` writer - DMA enable bit
20pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `DBLOCKSIZE` reader - Data block size
22pub type DBLOCKSIZE_R = crate::FieldReader;
23///Field `DBLOCKSIZE` writer - Data block size
24pub type DBLOCKSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25///Field `RWSTART` reader - Read wait start
26pub type RWSTART_R = crate::BitReader;
27///Field `RWSTART` writer - Read wait start
28pub type RWSTART_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `RWSTOP` reader - Read wait stop
30pub type RWSTOP_R = crate::BitReader;
31///Field `RWSTOP` writer - Read wait stop
32pub type RWSTOP_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `RWMOD` reader - Read wait mode
34pub type RWMOD_R = crate::BitReader;
35///Field `RWMOD` writer - Read wait mode
36pub type RWMOD_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `SDIOEN` reader - SD I/O enable functions
38pub type SDIOEN_R = crate::BitReader;
39///Field `SDIOEN` writer - SD I/O enable functions
40pub type SDIOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    ///Bit 0 - DTEN
43    #[inline(always)]
44    pub fn dten(&self) -> DTEN_R {
45        DTEN_R::new((self.bits & 1) != 0)
46    }
47    ///Bit 1 - Data transfer direction selection
48    #[inline(always)]
49    pub fn dtdir(&self) -> DTDIR_R {
50        DTDIR_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    ///Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
53    #[inline(always)]
54    pub fn dtmode(&self) -> DTMODE_R {
55        DTMODE_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    ///Bit 3 - DMA enable bit
58    #[inline(always)]
59    pub fn dmaen(&self) -> DMAEN_R {
60        DMAEN_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    ///Bits 4:7 - Data block size
63    #[inline(always)]
64    pub fn dblocksize(&self) -> DBLOCKSIZE_R {
65        DBLOCKSIZE_R::new(((self.bits >> 4) & 0x0f) as u8)
66    }
67    ///Bit 8 - Read wait start
68    #[inline(always)]
69    pub fn rwstart(&self) -> RWSTART_R {
70        RWSTART_R::new(((self.bits >> 8) & 1) != 0)
71    }
72    ///Bit 9 - Read wait stop
73    #[inline(always)]
74    pub fn rwstop(&self) -> RWSTOP_R {
75        RWSTOP_R::new(((self.bits >> 9) & 1) != 0)
76    }
77    ///Bit 10 - Read wait mode
78    #[inline(always)]
79    pub fn rwmod(&self) -> RWMOD_R {
80        RWMOD_R::new(((self.bits >> 10) & 1) != 0)
81    }
82    ///Bit 11 - SD I/O enable functions
83    #[inline(always)]
84    pub fn sdioen(&self) -> SDIOEN_R {
85        SDIOEN_R::new(((self.bits >> 11) & 1) != 0)
86    }
87}
88impl core::fmt::Debug for R {
89    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
90        f.debug_struct("DCTRL")
91            .field("sdioen", &self.sdioen())
92            .field("rwmod", &self.rwmod())
93            .field("rwstop", &self.rwstop())
94            .field("rwstart", &self.rwstart())
95            .field("dblocksize", &self.dblocksize())
96            .field("dmaen", &self.dmaen())
97            .field("dtmode", &self.dtmode())
98            .field("dtdir", &self.dtdir())
99            .field("dten", &self.dten())
100            .finish()
101    }
102}
103impl W {
104    ///Bit 0 - DTEN
105    #[inline(always)]
106    pub fn dten(&mut self) -> DTEN_W<DCTRLrs> {
107        DTEN_W::new(self, 0)
108    }
109    ///Bit 1 - Data transfer direction selection
110    #[inline(always)]
111    pub fn dtdir(&mut self) -> DTDIR_W<DCTRLrs> {
112        DTDIR_W::new(self, 1)
113    }
114    ///Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
115    #[inline(always)]
116    pub fn dtmode(&mut self) -> DTMODE_W<DCTRLrs> {
117        DTMODE_W::new(self, 2)
118    }
119    ///Bit 3 - DMA enable bit
120    #[inline(always)]
121    pub fn dmaen(&mut self) -> DMAEN_W<DCTRLrs> {
122        DMAEN_W::new(self, 3)
123    }
124    ///Bits 4:7 - Data block size
125    #[inline(always)]
126    pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<DCTRLrs> {
127        DBLOCKSIZE_W::new(self, 4)
128    }
129    ///Bit 8 - Read wait start
130    #[inline(always)]
131    pub fn rwstart(&mut self) -> RWSTART_W<DCTRLrs> {
132        RWSTART_W::new(self, 8)
133    }
134    ///Bit 9 - Read wait stop
135    #[inline(always)]
136    pub fn rwstop(&mut self) -> RWSTOP_W<DCTRLrs> {
137        RWSTOP_W::new(self, 9)
138    }
139    ///Bit 10 - Read wait mode
140    #[inline(always)]
141    pub fn rwmod(&mut self) -> RWMOD_W<DCTRLrs> {
142        RWMOD_W::new(self, 10)
143    }
144    ///Bit 11 - SD I/O enable functions
145    #[inline(always)]
146    pub fn sdioen(&mut self) -> SDIOEN_W<DCTRLrs> {
147        SDIOEN_W::new(self, 11)
148    }
149}
150/**data control register
151
152You can [`read`](crate::Reg::read) this register and get [`dctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:DCTRL)*/
155pub struct DCTRLrs;
156impl crate::RegisterSpec for DCTRLrs {
157    type Ux = u32;
158}
159///`read()` method returns [`dctrl::R`](R) reader structure
160impl crate::Readable for DCTRLrs {}
161///`write(|w| ..)` method takes [`dctrl::W`](W) writer structure
162impl crate::Writable for DCTRLrs {
163    type Safety = crate::Unsafe;
164}
165///`reset()` method sets DCTRL to value 0
166impl crate::Resettable for DCTRLrs {}
stm32f1_staging/stm32f107/sdio/dctrl.rs

stm32f1_staging/stm32f107/sdio/
dctrl.rs
