stm32f1_staging/stm32f107/
sdio.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    power: POWER,
6    clkcr: CLKCR,
7    arg: ARG,
8    cmd: CMD,
9    respcmd: RESPCMD,
10    resp1: RESP1,
11    resp2: RESP2,
12    resp3: RESP3,
13    resp4: RESP4,
14    dtimer: DTIMER,
15    dlen: DLEN,
16    dctrl: DCTRL,
17    dcount: DCOUNT,
18    sta: STA,
19    icr: ICR,
20    mask: MASK,
21    _reserved16: [u8; 0x08],
22    fifocnt: FIFOCNT,
23    _reserved17: [u8; 0x34],
24    fifo: FIFO,
25}
26impl RegisterBlock {
27    ///0x00 - power control register
28    #[inline(always)]
29    pub const fn power(&self) -> &POWER {
30        &self.power
31    }
32    ///0x04 - SDI clock control register
33    #[inline(always)]
34    pub const fn clkcr(&self) -> &CLKCR {
35        &self.clkcr
36    }
37    ///0x08 - argument register
38    #[inline(always)]
39    pub const fn arg(&self) -> &ARG {
40        &self.arg
41    }
42    ///0x0c - command register
43    #[inline(always)]
44    pub const fn cmd(&self) -> &CMD {
45        &self.cmd
46    }
47    ///0x10 - command response register
48    #[inline(always)]
49    pub const fn respcmd(&self) -> &RESPCMD {
50        &self.respcmd
51    }
52    ///0x14 - response 1..4 register
53    #[inline(always)]
54    pub const fn resp1(&self) -> &RESP1 {
55        &self.resp1
56    }
57    ///0x18 - response 1..4 register
58    #[inline(always)]
59    pub const fn resp2(&self) -> &RESP2 {
60        &self.resp2
61    }
62    ///0x1c - response 1..4 register
63    #[inline(always)]
64    pub const fn resp3(&self) -> &RESP3 {
65        &self.resp3
66    }
67    ///0x20 - response 1..4 register
68    #[inline(always)]
69    pub const fn resp4(&self) -> &RESP4 {
70        &self.resp4
71    }
72    ///0x24 - data timer register
73    #[inline(always)]
74    pub const fn dtimer(&self) -> &DTIMER {
75        &self.dtimer
76    }
77    ///0x28 - data length register
78    #[inline(always)]
79    pub const fn dlen(&self) -> &DLEN {
80        &self.dlen
81    }
82    ///0x2c - data control register
83    #[inline(always)]
84    pub const fn dctrl(&self) -> &DCTRL {
85        &self.dctrl
86    }
87    ///0x30 - data counter register
88    #[inline(always)]
89    pub const fn dcount(&self) -> &DCOUNT {
90        &self.dcount
91    }
92    ///0x34 - status register
93    #[inline(always)]
94    pub const fn sta(&self) -> &STA {
95        &self.sta
96    }
97    ///0x38 - interrupt clear register
98    #[inline(always)]
99    pub const fn icr(&self) -> &ICR {
100        &self.icr
101    }
102    ///0x3c - mask register
103    #[inline(always)]
104    pub const fn mask(&self) -> &MASK {
105        &self.mask
106    }
107    ///0x48 - FIFO counter register
108    #[inline(always)]
109    pub const fn fifocnt(&self) -> &FIFOCNT {
110        &self.fifocnt
111    }
112    ///0x80 - data FIFO register
113    #[inline(always)]
114    pub const fn fifo(&self) -> &FIFO {
115        &self.fifo
116    }
117}
118/**POWER (rw) register accessor: power control register
119
120You can [`read`](crate::Reg::read) this register and get [`power::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`power::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:POWER)
123
124For information about available fields see [`mod@power`] module*/
125pub type POWER = crate::Reg<power::POWERrs>;
126///power control register
127pub mod power;
128/**CLKCR (rw) register accessor: SDI clock control register
129
130You can [`read`](crate::Reg::read) this register and get [`clkcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
131
132See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:CLKCR)
133
134For information about available fields see [`mod@clkcr`] module*/
135pub type CLKCR = crate::Reg<clkcr::CLKCRrs>;
136///SDI clock control register
137pub mod clkcr;
138/**ARG (rw) register accessor: argument register
139
140You can [`read`](crate::Reg::read) this register and get [`arg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
141
142See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:ARG)
143
144For information about available fields see [`mod@arg`] module*/
145pub type ARG = crate::Reg<arg::ARGrs>;
146///argument register
147pub mod arg;
148/**CMD (rw) register accessor: command register
149
150You can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
151
152See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:CMD)
153
154For information about available fields see [`mod@cmd`] module*/
155pub type CMD = crate::Reg<cmd::CMDrs>;
156///command register
157pub mod cmd;
158/**RESPCMD (r) register accessor: command response register
159
160You can [`read`](crate::Reg::read) this register and get [`respcmd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:RESPCMD)
163
164For information about available fields see [`mod@respcmd`] module*/
165pub type RESPCMD = crate::Reg<respcmd::RESPCMDrs>;
166///command response register
167pub mod respcmd;
168/**RESP1 (r) register accessor: response 1..4 register
169
170You can [`read`](crate::Reg::read) this register and get [`resp1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
171
172See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:RESP1)
173
174For information about available fields see [`mod@resp1`] module*/
175pub type RESP1 = crate::Reg<resp1::RESP1rs>;
176///response 1..4 register
177pub mod resp1;
178/**RESP2 (r) register accessor: response 1..4 register
179
180You can [`read`](crate::Reg::read) this register and get [`resp2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
181
182See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:RESP2)
183
184For information about available fields see [`mod@resp2`] module*/
185pub type RESP2 = crate::Reg<resp2::RESP2rs>;
186///response 1..4 register
187pub mod resp2;
188/**RESP3 (r) register accessor: response 1..4 register
189
190You can [`read`](crate::Reg::read) this register and get [`resp3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
191
192See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:RESP3)
193
194For information about available fields see [`mod@resp3`] module*/
195pub type RESP3 = crate::Reg<resp3::RESP3rs>;
196///response 1..4 register
197pub mod resp3;
198/**RESP4 (r) register accessor: response 1..4 register
199
200You can [`read`](crate::Reg::read) this register and get [`resp4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
201
202See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:RESP4)
203
204For information about available fields see [`mod@resp4`] module*/
205pub type RESP4 = crate::Reg<resp4::RESP4rs>;
206///response 1..4 register
207pub mod resp4;
208/**DTIMER (rw) register accessor: data timer register
209
210You can [`read`](crate::Reg::read) this register and get [`dtimer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtimer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
211
212See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:DTIMER)
213
214For information about available fields see [`mod@dtimer`] module*/
215pub type DTIMER = crate::Reg<dtimer::DTIMERrs>;
216///data timer register
217pub mod dtimer;
218/**DLEN (rw) register accessor: data length register
219
220You can [`read`](crate::Reg::read) this register and get [`dlen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
221
222See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:DLEN)
223
224For information about available fields see [`mod@dlen`] module*/
225pub type DLEN = crate::Reg<dlen::DLENrs>;
226///data length register
227pub mod dlen;
228/**DCTRL (rw) register accessor: data control register
229
230You can [`read`](crate::Reg::read) this register and get [`dctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
231
232See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:DCTRL)
233
234For information about available fields see [`mod@dctrl`] module*/
235pub type DCTRL = crate::Reg<dctrl::DCTRLrs>;
236///data control register
237pub mod dctrl;
238/**DCOUNT (r) register accessor: data counter register
239
240You can [`read`](crate::Reg::read) this register and get [`dcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
241
242See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:DCOUNT)
243
244For information about available fields see [`mod@dcount`] module*/
245pub type DCOUNT = crate::Reg<dcount::DCOUNTrs>;
246///data counter register
247pub mod dcount;
248/**STA (r) register accessor: status register
249
250You can [`read`](crate::Reg::read) this register and get [`sta::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
251
252See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:STA)
253
254For information about available fields see [`mod@sta`] module*/
255pub type STA = crate::Reg<sta::STArs>;
256///status register
257pub mod sta;
258/**ICR (rw) register accessor: interrupt clear register
259
260You can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
261
262See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:ICR)
263
264For information about available fields see [`mod@icr`] module*/
265pub type ICR = crate::Reg<icr::ICRrs>;
266///interrupt clear register
267pub mod icr;
268/**MASK (rw) register accessor: mask register
269
270You can [`read`](crate::Reg::read) this register and get [`mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
271
272See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:MASK)
273
274For information about available fields see [`mod@mask`] module*/
275pub type MASK = crate::Reg<mask::MASKrs>;
276///mask register
277pub mod mask;
278/**FIFOCNT (r) register accessor: FIFO counter register
279
280You can [`read`](crate::Reg::read) this register and get [`fifocnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
281
282See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:FIFOCNT)
283
284For information about available fields see [`mod@fifocnt`] module*/
285pub type FIFOCNT = crate::Reg<fifocnt::FIFOCNTrs>;
286///FIFO counter register
287pub mod fifocnt;
288/**FIFO (rw) register accessor: data FIFO register
289
290You can [`read`](crate::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
291
292See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO:FIFO)
293
294For information about available fields see [`mod@fifo`] module*/
295pub type FIFO = crate::Reg<fifo::FIFOrs>;
296///data FIFO register
297pub mod fifo;
stm32f1_staging/stm32f107/sdio.rs

stm32f1_staging/stm32f107/
sdio.rs
