stm32f1_staging/stm32f107/
rcc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    cfgr: CFGR,
7    cir: CIR,
8    apb2rstr: APB2RSTR,
9    apb1rstr: APB1RSTR,
10    ahbenr: AHBENR,
11    apb2enr: APB2ENR,
12    apb1enr: APB1ENR,
13    bdcr: BDCR,
14    csr: CSR,
15    ahbrstr: AHBRSTR,
16    cfgr2: CFGR2,
17}
18impl RegisterBlock {
19    ///0x00 - Clock control register
20    #[inline(always)]
21    pub const fn cr(&self) -> &CR {
22        &self.cr
23    }
24    ///0x04 - Clock configuration register (RCC_CFGR)
25    #[inline(always)]
26    pub const fn cfgr(&self) -> &CFGR {
27        &self.cfgr
28    }
29    ///0x08 - Clock interrupt register (RCC_CIR)
30    #[inline(always)]
31    pub const fn cir(&self) -> &CIR {
32        &self.cir
33    }
34    ///0x0c - APB2 peripheral reset register (RCC_APB2RSTR)
35    #[inline(always)]
36    pub const fn apb2rstr(&self) -> &APB2RSTR {
37        &self.apb2rstr
38    }
39    ///0x10 - APB1 peripheral reset register (RCC_APB1RSTR)
40    #[inline(always)]
41    pub const fn apb1rstr(&self) -> &APB1RSTR {
42        &self.apb1rstr
43    }
44    ///0x14 - AHB Peripheral Clock enable register (RCC_AHBENR)
45    #[inline(always)]
46    pub const fn ahbenr(&self) -> &AHBENR {
47        &self.ahbenr
48    }
49    ///0x18 - APB2 peripheral clock enable register (RCC_APB2ENR)
50    #[inline(always)]
51    pub const fn apb2enr(&self) -> &APB2ENR {
52        &self.apb2enr
53    }
54    ///0x1c - APB1 peripheral clock enable register (RCC_APB1ENR)
55    #[inline(always)]
56    pub const fn apb1enr(&self) -> &APB1ENR {
57        &self.apb1enr
58    }
59    ///0x20 - Backup domain control register (RCC_BDCR)
60    #[inline(always)]
61    pub const fn bdcr(&self) -> &BDCR {
62        &self.bdcr
63    }
64    ///0x24 - Control/status register (RCC_CSR)
65    #[inline(always)]
66    pub const fn csr(&self) -> &CSR {
67        &self.csr
68    }
69    ///0x28 - AHB peripheral clock reset register (RCC_AHBRSTR)
70    #[inline(always)]
71    pub const fn ahbrstr(&self) -> &AHBRSTR {
72        &self.ahbrstr
73    }
74    ///0x2c - Clock configuration register2 (RCC_CFGR2)
75    #[inline(always)]
76    pub const fn cfgr2(&self) -> &CFGR2 {
77        &self.cfgr2
78    }
79}
80/**CR (rw) register accessor: Clock control register
81
82You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
83
84See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:CR)
85
86For information about available fields see [`mod@cr`] module*/
87pub type CR = crate::Reg<cr::CRrs>;
88///Clock control register
89pub mod cr;
90/**CFGR (rw) register accessor: Clock configuration register (RCC_CFGR)
91
92You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:CFGR)
95
96For information about available fields see [`mod@cfgr`] module*/
97pub type CFGR = crate::Reg<cfgr::CFGRrs>;
98///Clock configuration register (RCC_CFGR)
99pub mod cfgr;
100/**CIR (rw) register accessor: Clock interrupt register (RCC_CIR)
101
102You can [`read`](crate::Reg::read) this register and get [`cir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
103
104See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:CIR)
105
106For information about available fields see [`mod@cir`] module*/
107pub type CIR = crate::Reg<cir::CIRrs>;
108///Clock interrupt register (RCC_CIR)
109pub mod cir;
110/**APB2RSTR (rw) register accessor: APB2 peripheral reset register (RCC_APB2RSTR)
111
112You can [`read`](crate::Reg::read) this register and get [`apb2rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
113
114See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:APB2RSTR)
115
116For information about available fields see [`mod@apb2rstr`] module*/
117pub type APB2RSTR = crate::Reg<apb2rstr::APB2RSTRrs>;
118///APB2 peripheral reset register (RCC_APB2RSTR)
119pub mod apb2rstr;
120/**APB1RSTR (rw) register accessor: APB1 peripheral reset register (RCC_APB1RSTR)
121
122You can [`read`](crate::Reg::read) this register and get [`apb1rstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:APB1RSTR)
125
126For information about available fields see [`mod@apb1rstr`] module*/
127pub type APB1RSTR = crate::Reg<apb1rstr::APB1RSTRrs>;
128///APB1 peripheral reset register (RCC_APB1RSTR)
129pub mod apb1rstr;
130/**AHBENR (rw) register accessor: AHB Peripheral Clock enable register (RCC_AHBENR)
131
132You can [`read`](crate::Reg::read) this register and get [`ahbenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:AHBENR)
135
136For information about available fields see [`mod@ahbenr`] module*/
137pub type AHBENR = crate::Reg<ahbenr::AHBENRrs>;
138///AHB Peripheral Clock enable register (RCC_AHBENR)
139pub mod ahbenr;
140/**APB2ENR (rw) register accessor: APB2 peripheral clock enable register (RCC_APB2ENR)
141
142You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:APB2ENR)
145
146For information about available fields see [`mod@apb2enr`] module*/
147pub type APB2ENR = crate::Reg<apb2enr::APB2ENRrs>;
148///APB2 peripheral clock enable register (RCC_APB2ENR)
149pub mod apb2enr;
150/**APB1ENR (rw) register accessor: APB1 peripheral clock enable register (RCC_APB1ENR)
151
152You can [`read`](crate::Reg::read) this register and get [`apb1enr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:APB1ENR)
155
156For information about available fields see [`mod@apb1enr`] module*/
157pub type APB1ENR = crate::Reg<apb1enr::APB1ENRrs>;
158///APB1 peripheral clock enable register (RCC_APB1ENR)
159pub mod apb1enr;
160/**BDCR (rw) register accessor: Backup domain control register (RCC_BDCR)
161
162You can [`read`](crate::Reg::read) this register and get [`bdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
163
164See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:BDCR)
165
166For information about available fields see [`mod@bdcr`] module*/
167pub type BDCR = crate::Reg<bdcr::BDCRrs>;
168///Backup domain control register (RCC_BDCR)
169pub mod bdcr;
170/**CSR (rw) register accessor: Control/status register (RCC_CSR)
171
172You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
173
174See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:CSR)
175
176For information about available fields see [`mod@csr`] module*/
177pub type CSR = crate::Reg<csr::CSRrs>;
178///Control/status register (RCC_CSR)
179pub mod csr;
180/**AHBRSTR (rw) register accessor: AHB peripheral clock reset register (RCC_AHBRSTR)
181
182You can [`read`](crate::Reg::read) this register and get [`ahbrstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbrstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:AHBRSTR)
185
186For information about available fields see [`mod@ahbrstr`] module*/
187pub type AHBRSTR = crate::Reg<ahbrstr::AHBRSTRrs>;
188///AHB peripheral clock reset register (RCC_AHBRSTR)
189pub mod ahbrstr;
190/**CFGR2 (rw) register accessor: Clock configuration register2 (RCC_CFGR2)
191
192You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
193
194See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC:CFGR2)
195
196For information about available fields see [`mod@cfgr2`] module*/
197pub type CFGR2 = crate::Reg<cfgr2::CFGR2rs>;
198///Clock configuration register2 (RCC_CFGR2)
199pub mod cfgr2;
stm32f1_staging/stm32f107/rcc.rs

stm32f1_staging/stm32f107/
rcc.rs
