stm32f1_staging/stm32f107/adc1/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Analog watchdog flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AWDR {
11    ///0: No analog watchdog event occurred
12    NoEvent = 0,
13    ///1: Analog watchdog event occurred
14    Event = 1,
15}
16impl From<AWDR> for bool {
17    #[inline(always)]
18    fn from(variant: AWDR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `AWD` reader - Analog watchdog flag
23pub type AWD_R = crate::BitReader<AWDR>;
24impl AWD_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> AWDR {
28        match self.bits {
29            false => AWDR::NoEvent,
30            true => AWDR::Event,
31        }
32    }
33    ///No analog watchdog event occurred
34    #[inline(always)]
35    pub fn is_no_event(&self) -> bool {
36        *self == AWDR::NoEvent
37    }
38    ///Analog watchdog event occurred
39    #[inline(always)]
40    pub fn is_event(&self) -> bool {
41        *self == AWDR::Event
42    }
43}
44/**Analog watchdog flag
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum AWDW {
50    ///0: Clear the analog watchdog event flag
51    Clear = 0,
52}
53impl From<AWDW> for bool {
54    #[inline(always)]
55    fn from(variant: AWDW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `AWD` writer - Analog watchdog flag
60pub type AWD_W<'a, REG> = crate::BitWriter0C<'a, REG, AWDW>;
61impl<'a, REG> AWD_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear the analog watchdog event flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(AWDW::Clear)
69    }
70}
71/**Regular channel end of conversion
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum EOCR {
77    ///0: Conversion is not complete
78    NotComplete = 0,
79    ///1: Conversion complete
80    Complete = 1,
81}
82impl From<EOCR> for bool {
83    #[inline(always)]
84    fn from(variant: EOCR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `EOC` reader - Regular channel end of conversion
89pub type EOC_R = crate::BitReader<EOCR>;
90impl EOC_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> EOCR {
94        match self.bits {
95            false => EOCR::NotComplete,
96            true => EOCR::Complete,
97        }
98    }
99    ///Conversion is not complete
100    #[inline(always)]
101    pub fn is_not_complete(&self) -> bool {
102        *self == EOCR::NotComplete
103    }
104    ///Conversion complete
105    #[inline(always)]
106    pub fn is_complete(&self) -> bool {
107        *self == EOCR::Complete
108    }
109}
110/**Regular channel end of conversion
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum EOCW {
116    ///0: Clear End of conversion flag
117    Clear = 0,
118}
119impl From<EOCW> for bool {
120    #[inline(always)]
121    fn from(variant: EOCW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `EOC` writer - Regular channel end of conversion
126pub type EOC_W<'a, REG> = crate::BitWriter0C<'a, REG, EOCW>;
127impl<'a, REG> EOC_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Clear End of conversion flag
132    #[inline(always)]
133    pub fn clear(self) -> &'a mut crate::W<REG> {
134        self.variant(EOCW::Clear)
135    }
136}
137/**Injected channel end of conversion
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum JEOCR {
143    ///0: Conversion is not complete
144    NotComplete = 0,
145    ///1: Conversion complete
146    Complete = 1,
147}
148impl From<JEOCR> for bool {
149    #[inline(always)]
150    fn from(variant: JEOCR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `JEOC` reader - Injected channel end of conversion
155pub type JEOC_R = crate::BitReader<JEOCR>;
156impl JEOC_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> JEOCR {
160        match self.bits {
161            false => JEOCR::NotComplete,
162            true => JEOCR::Complete,
163        }
164    }
165    ///Conversion is not complete
166    #[inline(always)]
167    pub fn is_not_complete(&self) -> bool {
168        *self == JEOCR::NotComplete
169    }
170    ///Conversion complete
171    #[inline(always)]
172    pub fn is_complete(&self) -> bool {
173        *self == JEOCR::Complete
174    }
175}
176/**Injected channel end of conversion
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum JEOCW {
182    ///0: Clear Injected channel end of conversion flag
183    Clear = 0,
184}
185impl From<JEOCW> for bool {
186    #[inline(always)]
187    fn from(variant: JEOCW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `JEOC` writer - Injected channel end of conversion
192pub type JEOC_W<'a, REG> = crate::BitWriter0C<'a, REG, JEOCW>;
193impl<'a, REG> JEOC_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Clear Injected channel end of conversion flag
198    #[inline(always)]
199    pub fn clear(self) -> &'a mut crate::W<REG> {
200        self.variant(JEOCW::Clear)
201    }
202}
203/**Injected channel start flag
204
205Value on reset: 0*/
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum JSTRTR {
209    ///0: No injected group conversion started
210    NotStarted = 0,
211    ///1: Injected group conversion has started
212    Started = 1,
213}
214impl From<JSTRTR> for bool {
215    #[inline(always)]
216    fn from(variant: JSTRTR) -> Self {
217        variant as u8 != 0
218    }
219}
220///Field `JSTRT` reader - Injected channel start flag
221pub type JSTRT_R = crate::BitReader<JSTRTR>;
222impl JSTRT_R {
223    ///Get enumerated values variant
224    #[inline(always)]
225    pub const fn variant(&self) -> JSTRTR {
226        match self.bits {
227            false => JSTRTR::NotStarted,
228            true => JSTRTR::Started,
229        }
230    }
231    ///No injected group conversion started
232    #[inline(always)]
233    pub fn is_not_started(&self) -> bool {
234        *self == JSTRTR::NotStarted
235    }
236    ///Injected group conversion has started
237    #[inline(always)]
238    pub fn is_started(&self) -> bool {
239        *self == JSTRTR::Started
240    }
241}
242/**Injected channel start flag
243
244Value on reset: 0*/
245#[cfg_attr(feature = "defmt", derive(defmt::Format))]
246#[derive(Clone, Copy, Debug, PartialEq, Eq)]
247pub enum JSTRTW {
248    ///0: Clear Injected channel Start flag
249    Clear = 0,
250}
251impl From<JSTRTW> for bool {
252    #[inline(always)]
253    fn from(variant: JSTRTW) -> Self {
254        variant as u8 != 0
255    }
256}
257///Field `JSTRT` writer - Injected channel start flag
258pub type JSTRT_W<'a, REG> = crate::BitWriter0C<'a, REG, JSTRTW>;
259impl<'a, REG> JSTRT_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    ///Clear Injected channel Start flag
264    #[inline(always)]
265    pub fn clear(self) -> &'a mut crate::W<REG> {
266        self.variant(JSTRTW::Clear)
267    }
268}
269/**Regular channel start flag
270
271Value on reset: 0*/
272#[cfg_attr(feature = "defmt", derive(defmt::Format))]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum STRTR {
275    ///0: No regular channel conversion started
276    NotStarted = 0,
277    ///1: Regular channel conversion has started
278    Started = 1,
279}
280impl From<STRTR> for bool {
281    #[inline(always)]
282    fn from(variant: STRTR) -> Self {
283        variant as u8 != 0
284    }
285}
286///Field `STRT` reader - Regular channel start flag
287pub type STRT_R = crate::BitReader<STRTR>;
288impl STRT_R {
289    ///Get enumerated values variant
290    #[inline(always)]
291    pub const fn variant(&self) -> STRTR {
292        match self.bits {
293            false => STRTR::NotStarted,
294            true => STRTR::Started,
295        }
296    }
297    ///No regular channel conversion started
298    #[inline(always)]
299    pub fn is_not_started(&self) -> bool {
300        *self == STRTR::NotStarted
301    }
302    ///Regular channel conversion has started
303    #[inline(always)]
304    pub fn is_started(&self) -> bool {
305        *self == STRTR::Started
306    }
307}
308/**Regular channel start flag
309
310Value on reset: 0*/
311#[cfg_attr(feature = "defmt", derive(defmt::Format))]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313pub enum STRTW {
314    ///0: Clear the Regular channel Start flag
315    Clear = 0,
316}
317impl From<STRTW> for bool {
318    #[inline(always)]
319    fn from(variant: STRTW) -> Self {
320        variant as u8 != 0
321    }
322}
323///Field `STRT` writer - Regular channel start flag
324pub type STRT_W<'a, REG> = crate::BitWriter0C<'a, REG, STRTW>;
325impl<'a, REG> STRT_W<'a, REG>
326where
327    REG: crate::Writable + crate::RegisterSpec,
328{
329    ///Clear the Regular channel Start flag
330    #[inline(always)]
331    pub fn clear(self) -> &'a mut crate::W<REG> {
332        self.variant(STRTW::Clear)
333    }
334}
335impl R {
336    ///Bit 0 - Analog watchdog flag
337    #[inline(always)]
338    pub fn awd(&self) -> AWD_R {
339        AWD_R::new((self.bits & 1) != 0)
340    }
341    ///Bit 1 - Regular channel end of conversion
342    #[inline(always)]
343    pub fn eoc(&self) -> EOC_R {
344        EOC_R::new(((self.bits >> 1) & 1) != 0)
345    }
346    ///Bit 2 - Injected channel end of conversion
347    #[inline(always)]
348    pub fn jeoc(&self) -> JEOC_R {
349        JEOC_R::new(((self.bits >> 2) & 1) != 0)
350    }
351    ///Bit 3 - Injected channel start flag
352    #[inline(always)]
353    pub fn jstrt(&self) -> JSTRT_R {
354        JSTRT_R::new(((self.bits >> 3) & 1) != 0)
355    }
356    ///Bit 4 - Regular channel start flag
357    #[inline(always)]
358    pub fn strt(&self) -> STRT_R {
359        STRT_R::new(((self.bits >> 4) & 1) != 0)
360    }
361}
362impl core::fmt::Debug for R {
363    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
364        f.debug_struct("SR")
365            .field("strt", &self.strt())
366            .field("jstrt", &self.jstrt())
367            .field("jeoc", &self.jeoc())
368            .field("eoc", &self.eoc())
369            .field("awd", &self.awd())
370            .finish()
371    }
372}
373impl W {
374    ///Bit 0 - Analog watchdog flag
375    #[inline(always)]
376    pub fn awd(&mut self) -> AWD_W<SRrs> {
377        AWD_W::new(self, 0)
378    }
379    ///Bit 1 - Regular channel end of conversion
380    #[inline(always)]
381    pub fn eoc(&mut self) -> EOC_W<SRrs> {
382        EOC_W::new(self, 1)
383    }
384    ///Bit 2 - Injected channel end of conversion
385    #[inline(always)]
386    pub fn jeoc(&mut self) -> JEOC_W<SRrs> {
387        JEOC_W::new(self, 2)
388    }
389    ///Bit 3 - Injected channel start flag
390    #[inline(always)]
391    pub fn jstrt(&mut self) -> JSTRT_W<SRrs> {
392        JSTRT_W::new(self, 3)
393    }
394    ///Bit 4 - Regular channel start flag
395    #[inline(always)]
396    pub fn strt(&mut self) -> STRT_W<SRrs> {
397        STRT_W::new(self, 4)
398    }
399}
400/**status register
401
402You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
403
404See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC1:SR)*/
405pub struct SRrs;
406impl crate::RegisterSpec for SRrs {
407    type Ux = u32;
408}
409///`read()` method returns [`sr::R`](R) reader structure
410impl crate::Readable for SRrs {}
411///`write(|w| ..)` method takes [`sr::W`](W) writer structure
412impl crate::Writable for SRrs {
413    type Safety = crate::Unsafe;
414    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1f;
415}
416///`reset()` method sets SR to value 0
417impl crate::Resettable for SRrs {}
stm32f1_staging/stm32f107/adc1/sr.rs

stm32f1_staging/stm32f107/adc1/
sr.rs
