stm32f1_staging/stm32f103/
usb.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    epr: [EPR; 8],
6    _reserved1: [u8; 0x20],
7    cntr: CNTR,
8    istr: ISTR,
9    fnr: FNR,
10    daddr: DADDR,
11    btable: BTABLE,
12}
13impl RegisterBlock {
14    ///0x00..0x20 - endpoint %s register
15    #[inline(always)]
16    pub const fn epr(&self, n: usize) -> &EPR {
17        &self.epr[n]
18    }
19    ///Iterator for array of:
20    ///0x00..0x20 - endpoint %s register
21    #[inline(always)]
22    pub fn epr_iter(&self) -> impl Iterator<Item = &EPR> {
23        self.epr.iter()
24    }
25    ///0x00 - endpoint 0 register
26    #[inline(always)]
27    pub const fn ep0r(&self) -> &EPR {
28        self.epr(0)
29    }
30    ///0x04 - endpoint 1 register
31    #[inline(always)]
32    pub const fn ep1r(&self) -> &EPR {
33        self.epr(1)
34    }
35    ///0x08 - endpoint 2 register
36    #[inline(always)]
37    pub const fn ep2r(&self) -> &EPR {
38        self.epr(2)
39    }
40    ///0x0c - endpoint 3 register
41    #[inline(always)]
42    pub const fn ep3r(&self) -> &EPR {
43        self.epr(3)
44    }
45    ///0x10 - endpoint 4 register
46    #[inline(always)]
47    pub const fn ep4r(&self) -> &EPR {
48        self.epr(4)
49    }
50    ///0x14 - endpoint 5 register
51    #[inline(always)]
52    pub const fn ep5r(&self) -> &EPR {
53        self.epr(5)
54    }
55    ///0x18 - endpoint 6 register
56    #[inline(always)]
57    pub const fn ep6r(&self) -> &EPR {
58        self.epr(6)
59    }
60    ///0x1c - endpoint 7 register
61    #[inline(always)]
62    pub const fn ep7r(&self) -> &EPR {
63        self.epr(7)
64    }
65    ///0x40 - control register
66    #[inline(always)]
67    pub const fn cntr(&self) -> &CNTR {
68        &self.cntr
69    }
70    ///0x44 - interrupt status register
71    #[inline(always)]
72    pub const fn istr(&self) -> &ISTR {
73        &self.istr
74    }
75    ///0x48 - frame number register
76    #[inline(always)]
77    pub const fn fnr(&self) -> &FNR {
78        &self.fnr
79    }
80    ///0x4c - device address
81    #[inline(always)]
82    pub const fn daddr(&self) -> &DADDR {
83        &self.daddr
84    }
85    ///0x50 - Buffer table address
86    #[inline(always)]
87    pub const fn btable(&self) -> &BTABLE {
88        &self.btable
89    }
90}
91/**EPR (rw) register accessor: endpoint %s register
92
93You can [`read`](crate::Reg::read) this register and get [`epr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`epr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
94
95See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USB:EP[0]R)
96
97For information about available fields see [`mod@epr`] module*/
98pub type EPR = crate::Reg<epr::EPRrs>;
99///endpoint %s register
100pub mod epr;
101/**CNTR (rw) register accessor: control register
102
103You can [`read`](crate::Reg::read) this register and get [`cntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
104
105See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USB:CNTR)
106
107For information about available fields see [`mod@cntr`] module*/
108pub type CNTR = crate::Reg<cntr::CNTRrs>;
109///control register
110pub mod cntr;
111/**ISTR (rw) register accessor: interrupt status register
112
113You can [`read`](crate::Reg::read) this register and get [`istr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`istr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
114
115See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USB:ISTR)
116
117For information about available fields see [`mod@istr`] module*/
118pub type ISTR = crate::Reg<istr::ISTRrs>;
119///interrupt status register
120pub mod istr;
121/**FNR (r) register accessor: frame number register
122
123You can [`read`](crate::Reg::read) this register and get [`fnr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
124
125See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USB:FNR)
126
127For information about available fields see [`mod@fnr`] module*/
128pub type FNR = crate::Reg<fnr::FNRrs>;
129///frame number register
130pub mod fnr;
131/**DADDR (rw) register accessor: device address
132
133You can [`read`](crate::Reg::read) this register and get [`daddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
134
135See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USB:DADDR)
136
137For information about available fields see [`mod@daddr`] module*/
138pub type DADDR = crate::Reg<daddr::DADDRrs>;
139///device address
140pub mod daddr;
141/**BTABLE (rw) register accessor: Buffer table address
142
143You can [`read`](crate::Reg::read) this register and get [`btable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
144
145See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USB:BTABLE)
146
147For information about available fields see [`mod@btable`] module*/
148pub type BTABLE = crate::Reg<btable::BTABLErs>;
149///Buffer table address
150pub mod btable;
stm32f1_staging/stm32f103/usb.rs

stm32f1_staging/stm32f103/
usb.rs
