stm32f1_staging/stm32f103/rtc/
divl.rs

1///Register `DIVL` reader
2pub type R = crate::R<DIVLrs>;
3///Field `DIVL` reader - RTC prescaler divider register Low
4pub type DIVL_R = crate::FieldReader<u16>;
5impl R {
6    ///Bits 0:15 - RTC prescaler divider register Low
7    #[inline(always)]
8    pub fn divl(&self) -> DIVL_R {
9        DIVL_R::new((self.bits & 0xffff) as u16)
10    }
11}
12impl core::fmt::Debug for R {
13    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
14        f.debug_struct("DIVL").field("divl", &self.divl()).finish()
15    }
16}
17/**RTC Prescaler Divider Register Low
18
19You can [`read`](crate::Reg::read) this register and get [`divl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
20
21See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RTC:DIVL)*/
22pub struct DIVLrs;
23impl crate::RegisterSpec for DIVLrs {
24    type Ux = u32;
25}
26///`read()` method returns [`divl::R`](R) reader structure
27impl crate::Readable for DIVLrs {}
28///`reset()` method sets DIVL to value 0x8000
29impl crate::Resettable for DIVLrs {
30    const RESET_VALUE: u32 = 0x8000;
31}
stm32f1_staging/stm32f103/rtc/divl.rs

stm32f1_staging/stm32f103/rtc/
divl.rs
