stm32f1_staging/stm32f103/rtc/
crl.rs

1///Register `CRL` reader
2pub type R = crate::R<CRLrs>;
3///Register `CRL` writer
4pub type W = crate::W<CRLrs>;
5/**Second Flag
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum SECFR {
11    ///0: Second flag condition not met
12    NoPrescalerOverflow = 0,
13    ///1: Second flag condition met
14    PrescalerOverflow = 1,
15}
16impl From<SECFR> for bool {
17    #[inline(always)]
18    fn from(variant: SECFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `SECF` reader - Second Flag
23pub type SECF_R = crate::BitReader<SECFR>;
24impl SECF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> SECFR {
28        match self.bits {
29            false => SECFR::NoPrescalerOverflow,
30            true => SECFR::PrescalerOverflow,
31        }
32    }
33    ///Second flag condition not met
34    #[inline(always)]
35    pub fn is_no_prescaler_overflow(&self) -> bool {
36        *self == SECFR::NoPrescalerOverflow
37    }
38    ///Second flag condition met
39    #[inline(always)]
40    pub fn is_prescaler_overflow(&self) -> bool {
41        *self == SECFR::PrescalerOverflow
42    }
43}
44/**Second Flag
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum CLEAR {
50    ///0: Clear flag
51    Clear = 0,
52}
53impl From<CLEAR> for bool {
54    #[inline(always)]
55    fn from(variant: CLEAR) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `SECF` writer - Second Flag
60pub type SECF_W<'a, REG> = crate::BitWriter0C<'a, REG, CLEAR>;
61impl<'a, REG> SECF_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(CLEAR::Clear)
69    }
70}
71/**Alarm Flag
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum ALRFR {
77    ///0: Alarm not detected
78    NoAlarm = 0,
79    ///1: Alarm detected
80    Alarm = 1,
81}
82impl From<ALRFR> for bool {
83    #[inline(always)]
84    fn from(variant: ALRFR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `ALRF` reader - Alarm Flag
89pub type ALRF_R = crate::BitReader<ALRFR>;
90impl ALRF_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> ALRFR {
94        match self.bits {
95            false => ALRFR::NoAlarm,
96            true => ALRFR::Alarm,
97        }
98    }
99    ///Alarm not detected
100    #[inline(always)]
101    pub fn is_no_alarm(&self) -> bool {
102        *self == ALRFR::NoAlarm
103    }
104    ///Alarm detected
105    #[inline(always)]
106    pub fn is_alarm(&self) -> bool {
107        *self == ALRFR::Alarm
108    }
109}
110///Field `ALRF` writer - Alarm Flag
111pub use SECF_W as ALRF_W;
112/**Overflow Flag
113
114Value on reset: 0*/
115#[cfg_attr(feature = "defmt", derive(defmt::Format))]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum OWFR {
118    ///0: Overflow not detected
119    NoOverflow = 0,
120    ///1: 32-bit programmable counter overflow occurred
121    Overflow = 1,
122}
123impl From<OWFR> for bool {
124    #[inline(always)]
125    fn from(variant: OWFR) -> Self {
126        variant as u8 != 0
127    }
128}
129///Field `OWF` reader - Overflow Flag
130pub type OWF_R = crate::BitReader<OWFR>;
131impl OWF_R {
132    ///Get enumerated values variant
133    #[inline(always)]
134    pub const fn variant(&self) -> OWFR {
135        match self.bits {
136            false => OWFR::NoOverflow,
137            true => OWFR::Overflow,
138        }
139    }
140    ///Overflow not detected
141    #[inline(always)]
142    pub fn is_no_overflow(&self) -> bool {
143        *self == OWFR::NoOverflow
144    }
145    ///32-bit programmable counter overflow occurred
146    #[inline(always)]
147    pub fn is_overflow(&self) -> bool {
148        *self == OWFR::Overflow
149    }
150}
151///Field `OWF` writer - Overflow Flag
152pub use SECF_W as OWF_W;
153/**Registers Synchronized Flag
154
155Value on reset: 0*/
156#[cfg_attr(feature = "defmt", derive(defmt::Format))]
157#[derive(Clone, Copy, Debug, PartialEq, Eq)]
158pub enum RSFR {
159    ///0: Registers not yet synchronized
160    NotSynchronized = 0,
161    ///1: Registers synchronized
162    Synchronized = 1,
163}
164impl From<RSFR> for bool {
165    #[inline(always)]
166    fn from(variant: RSFR) -> Self {
167        variant as u8 != 0
168    }
169}
170///Field `RSF` reader - Registers Synchronized Flag
171pub type RSF_R = crate::BitReader<RSFR>;
172impl RSF_R {
173    ///Get enumerated values variant
174    #[inline(always)]
175    pub const fn variant(&self) -> RSFR {
176        match self.bits {
177            false => RSFR::NotSynchronized,
178            true => RSFR::Synchronized,
179        }
180    }
181    ///Registers not yet synchronized
182    #[inline(always)]
183    pub fn is_not_synchronized(&self) -> bool {
184        *self == RSFR::NotSynchronized
185    }
186    ///Registers synchronized
187    #[inline(always)]
188    pub fn is_synchronized(&self) -> bool {
189        *self == RSFR::Synchronized
190    }
191}
192///Field `RSF` writer - Registers Synchronized Flag
193pub use SECF_W as RSF_W;
194/**Configuration Flag
195
196Value on reset: 0*/
197#[cfg_attr(feature = "defmt", derive(defmt::Format))]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum CNF {
200    ///0: Exit configuration mode (start update of RTC registers)
201    Exit = 0,
202    ///1: Enter configuration mode
203    Enter = 1,
204}
205impl From<CNF> for bool {
206    #[inline(always)]
207    fn from(variant: CNF) -> Self {
208        variant as u8 != 0
209    }
210}
211///Field `CNF` reader - Configuration Flag
212pub type CNF_R = crate::BitReader<CNF>;
213impl CNF_R {
214    ///Get enumerated values variant
215    #[inline(always)]
216    pub const fn variant(&self) -> CNF {
217        match self.bits {
218            false => CNF::Exit,
219            true => CNF::Enter,
220        }
221    }
222    ///Exit configuration mode (start update of RTC registers)
223    #[inline(always)]
224    pub fn is_exit(&self) -> bool {
225        *self == CNF::Exit
226    }
227    ///Enter configuration mode
228    #[inline(always)]
229    pub fn is_enter(&self) -> bool {
230        *self == CNF::Enter
231    }
232}
233///Field `CNF` writer - Configuration Flag
234pub type CNF_W<'a, REG> = crate::BitWriter<'a, REG, CNF>;
235impl<'a, REG> CNF_W<'a, REG>
236where
237    REG: crate::Writable + crate::RegisterSpec,
238{
239    ///Exit configuration mode (start update of RTC registers)
240    #[inline(always)]
241    pub fn exit(self) -> &'a mut crate::W<REG> {
242        self.variant(CNF::Exit)
243    }
244    ///Enter configuration mode
245    #[inline(always)]
246    pub fn enter(self) -> &'a mut crate::W<REG> {
247        self.variant(CNF::Enter)
248    }
249}
250/**RTC operation OFF
251
252Value on reset: 1*/
253#[cfg_attr(feature = "defmt", derive(defmt::Format))]
254#[derive(Clone, Copy, Debug, PartialEq, Eq)]
255pub enum RTOFF {
256    ///0: Last write operation on RTC registers is still ongoing
257    Enabled = 0,
258    ///1: Last write operation on RTC registers terminated
259    Disabled = 1,
260}
261impl From<RTOFF> for bool {
262    #[inline(always)]
263    fn from(variant: RTOFF) -> Self {
264        variant as u8 != 0
265    }
266}
267///Field `RTOFF` reader - RTC operation OFF
268pub type RTOFF_R = crate::BitReader<RTOFF>;
269impl RTOFF_R {
270    ///Get enumerated values variant
271    #[inline(always)]
272    pub const fn variant(&self) -> RTOFF {
273        match self.bits {
274            false => RTOFF::Enabled,
275            true => RTOFF::Disabled,
276        }
277    }
278    ///Last write operation on RTC registers is still ongoing
279    #[inline(always)]
280    pub fn is_enabled(&self) -> bool {
281        *self == RTOFF::Enabled
282    }
283    ///Last write operation on RTC registers terminated
284    #[inline(always)]
285    pub fn is_disabled(&self) -> bool {
286        *self == RTOFF::Disabled
287    }
288}
289impl R {
290    ///Bit 0 - Second Flag
291    #[inline(always)]
292    pub fn secf(&self) -> SECF_R {
293        SECF_R::new((self.bits & 1) != 0)
294    }
295    ///Bit 1 - Alarm Flag
296    #[inline(always)]
297    pub fn alrf(&self) -> ALRF_R {
298        ALRF_R::new(((self.bits >> 1) & 1) != 0)
299    }
300    ///Bit 2 - Overflow Flag
301    #[inline(always)]
302    pub fn owf(&self) -> OWF_R {
303        OWF_R::new(((self.bits >> 2) & 1) != 0)
304    }
305    ///Bit 3 - Registers Synchronized Flag
306    #[inline(always)]
307    pub fn rsf(&self) -> RSF_R {
308        RSF_R::new(((self.bits >> 3) & 1) != 0)
309    }
310    ///Bit 4 - Configuration Flag
311    #[inline(always)]
312    pub fn cnf(&self) -> CNF_R {
313        CNF_R::new(((self.bits >> 4) & 1) != 0)
314    }
315    ///Bit 5 - RTC operation OFF
316    #[inline(always)]
317    pub fn rtoff(&self) -> RTOFF_R {
318        RTOFF_R::new(((self.bits >> 5) & 1) != 0)
319    }
320}
321impl core::fmt::Debug for R {
322    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
323        f.debug_struct("CRL")
324            .field("secf", &self.secf())
325            .field("alrf", &self.alrf())
326            .field("owf", &self.owf())
327            .field("rsf", &self.rsf())
328            .field("cnf", &self.cnf())
329            .field("rtoff", &self.rtoff())
330            .finish()
331    }
332}
333impl W {
334    ///Bit 0 - Second Flag
335    #[inline(always)]
336    pub fn secf(&mut self) -> SECF_W<CRLrs> {
337        SECF_W::new(self, 0)
338    }
339    ///Bit 1 - Alarm Flag
340    #[inline(always)]
341    pub fn alrf(&mut self) -> ALRF_W<CRLrs> {
342        ALRF_W::new(self, 1)
343    }
344    ///Bit 2 - Overflow Flag
345    #[inline(always)]
346    pub fn owf(&mut self) -> OWF_W<CRLrs> {
347        OWF_W::new(self, 2)
348    }
349    ///Bit 3 - Registers Synchronized Flag
350    #[inline(always)]
351    pub fn rsf(&mut self) -> RSF_W<CRLrs> {
352        RSF_W::new(self, 3)
353    }
354    ///Bit 4 - Configuration Flag
355    #[inline(always)]
356    pub fn cnf(&mut self) -> CNF_W<CRLrs> {
357        CNF_W::new(self, 4)
358    }
359}
360/**RTC Control Register Low
361
362You can [`read`](crate::Reg::read) this register and get [`crl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
363
364See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RTC:CRL)*/
365pub struct CRLrs;
366impl crate::RegisterSpec for CRLrs {
367    type Ux = u32;
368}
369///`read()` method returns [`crl::R`](R) reader structure
370impl crate::Readable for CRLrs {}
371///`write(|w| ..)` method takes [`crl::W`](W) writer structure
372impl crate::Writable for CRLrs {
373    type Safety = crate::Unsafe;
374    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f;
375}
376///`reset()` method sets CRL to value 0x20
377impl crate::Resettable for CRLrs {
378    const RESET_VALUE: u32 = 0x20;
379}
stm32f1_staging/stm32f103/rtc/crl.rs

stm32f1_staging/stm32f103/rtc/
crl.rs
