stm32f1_staging/stm32f103/
mod.rs

1/*!Peripheral access API for STM32F103 microcontrollers (generated using svd2rust v0.36.1 (a85deda 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{
16    CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU,
17};
18#[cfg(feature = "rt")]
19pub use cortex_m_rt::interrupt;
20#[cfg(feature = "rt")]
21extern "C" {
22    fn WWDG();
23    fn PVD();
24    fn TAMPER();
25    fn RTC();
26    fn FLASH();
27    fn RCC();
28    fn EXTI0();
29    fn EXTI1();
30    fn EXTI2();
31    fn EXTI3();
32    fn EXTI4();
33    fn DMA1_CHANNEL1();
34    fn DMA1_CHANNEL2();
35    fn DMA1_CHANNEL3();
36    fn DMA1_CHANNEL4();
37    fn DMA1_CHANNEL5();
38    fn DMA1_CHANNEL6();
39    fn DMA1_CHANNEL7();
40    fn ADC1_2();
41    fn USB_HP_CAN_TX();
42    fn USB_LP_CAN_RX0();
43    fn CAN_RX1();
44    fn CAN_SCE();
45    fn EXTI9_5();
46    fn TIM1_BRK();
47    fn TIM1_UP();
48    fn TIM1_TRG_COM();
49    fn TIM1_CC();
50    fn TIM2();
51    fn TIM3();
52    fn TIM4();
53    fn I2C1_EV();
54    fn I2C1_ER();
55    fn I2C2_EV();
56    fn I2C2_ER();
57    fn SPI1();
58    fn SPI2();
59    fn USART1();
60    fn USART2();
61    fn USART3();
62    fn EXTI15_10();
63    fn RTCALARM();
64    fn TIM8_BRK();
65    fn TIM8_UP();
66    fn TIM8_TRG_COM();
67    fn TIM8_CC();
68    fn ADC3();
69    fn FSMC();
70    fn SDIO();
71    fn TIM5();
72    fn SPI3();
73    fn UART4();
74    fn UART5();
75    fn TIM6();
76    fn TIM7();
77    fn DMA2_CHANNEL1();
78    fn DMA2_CHANNEL2();
79    fn DMA2_CHANNEL3();
80    fn DMA2_CHANNEL4_5();
81}
82#[doc(hidden)]
83#[repr(C)]
84pub union Vector {
85    _handler: unsafe extern "C" fn(),
86    _reserved: u32,
87}
88#[cfg(feature = "rt")]
89#[doc(hidden)]
90#[link_section = ".vector_table.interrupts"]
91#[no_mangle]
92pub static __INTERRUPTS: [Vector; 60] = [
93    Vector { _handler: WWDG },
94    Vector { _handler: PVD },
95    Vector { _handler: TAMPER },
96    Vector { _handler: RTC },
97    Vector { _handler: FLASH },
98    Vector { _handler: RCC },
99    Vector { _handler: EXTI0 },
100    Vector { _handler: EXTI1 },
101    Vector { _handler: EXTI2 },
102    Vector { _handler: EXTI3 },
103    Vector { _handler: EXTI4 },
104    Vector { _handler: DMA1_CHANNEL1 },
105    Vector { _handler: DMA1_CHANNEL2 },
106    Vector { _handler: DMA1_CHANNEL3 },
107    Vector { _handler: DMA1_CHANNEL4 },
108    Vector { _handler: DMA1_CHANNEL5 },
109    Vector { _handler: DMA1_CHANNEL6 },
110    Vector { _handler: DMA1_CHANNEL7 },
111    Vector { _handler: ADC1_2 },
112    Vector { _handler: USB_HP_CAN_TX },
113    Vector { _handler: USB_LP_CAN_RX0 },
114    Vector { _handler: CAN_RX1 },
115    Vector { _handler: CAN_SCE },
116    Vector { _handler: EXTI9_5 },
117    Vector { _handler: TIM1_BRK },
118    Vector { _handler: TIM1_UP },
119    Vector { _handler: TIM1_TRG_COM },
120    Vector { _handler: TIM1_CC },
121    Vector { _handler: TIM2 },
122    Vector { _handler: TIM3 },
123    Vector { _handler: TIM4 },
124    Vector { _handler: I2C1_EV },
125    Vector { _handler: I2C1_ER },
126    Vector { _handler: I2C2_EV },
127    Vector { _handler: I2C2_ER },
128    Vector { _handler: SPI1 },
129    Vector { _handler: SPI2 },
130    Vector { _handler: USART1 },
131    Vector { _handler: USART2 },
132    Vector { _handler: USART3 },
133    Vector { _handler: EXTI15_10 },
134    Vector { _handler: RTCALARM },
135    Vector { _reserved: 0 },
136    Vector { _handler: TIM8_BRK },
137    Vector { _handler: TIM8_UP },
138    Vector { _handler: TIM8_TRG_COM },
139    Vector { _handler: TIM8_CC },
140    Vector { _handler: ADC3 },
141    Vector { _handler: FSMC },
142    Vector { _handler: SDIO },
143    Vector { _handler: TIM5 },
144    Vector { _handler: SPI3 },
145    Vector { _handler: UART4 },
146    Vector { _handler: UART5 },
147    Vector { _handler: TIM6 },
148    Vector { _handler: TIM7 },
149    Vector { _handler: DMA2_CHANNEL1 },
150    Vector { _handler: DMA2_CHANNEL2 },
151    Vector { _handler: DMA2_CHANNEL3 },
152    Vector {
153        _handler: DMA2_CHANNEL4_5,
154    },
155];
156///Enumeration of all the interrupts.
157#[cfg_attr(feature = "defmt", derive(defmt::Format))]
158#[derive(Copy, Clone, Debug, PartialEq, Eq)]
159#[repr(u16)]
160pub enum Interrupt {
161    ///0 - Window Watchdog interrupt
162    WWDG = 0,
163    ///1 - PVD through EXTI line detection interrupt
164    PVD = 1,
165    ///2 - Tamper interrupt
166    TAMPER = 2,
167    ///3 - RTC global interrupt
168    RTC = 3,
169    ///4 - Flash global interrupt
170    FLASH = 4,
171    ///5 - RCC global interrupt
172    RCC = 5,
173    ///6 - EXTI Line0 interrupt
174    EXTI0 = 6,
175    ///7 - EXTI Line1 interrupt
176    EXTI1 = 7,
177    ///8 - EXTI Line2 interrupt
178    EXTI2 = 8,
179    ///9 - EXTI Line3 interrupt
180    EXTI3 = 9,
181    ///10 - EXTI Line4 interrupt
182    EXTI4 = 10,
183    ///11 - DMA1 Channel1 global interrupt
184    DMA1_CHANNEL1 = 11,
185    ///12 - DMA1 Channel2 global interrupt
186    DMA1_CHANNEL2 = 12,
187    ///13 - DMA1 Channel3 global interrupt
188    DMA1_CHANNEL3 = 13,
189    ///14 - DMA1 Channel4 global interrupt
190    DMA1_CHANNEL4 = 14,
191    ///15 - DMA1 Channel5 global interrupt
192    DMA1_CHANNEL5 = 15,
193    ///16 - DMA1 Channel6 global interrupt
194    DMA1_CHANNEL6 = 16,
195    ///17 - DMA1 Channel7 global interrupt
196    DMA1_CHANNEL7 = 17,
197    ///18 - ADC1 and ADC2 global interrupt
198    ADC1_2 = 18,
199    ///19 - USB High Priority or CAN TX interrupts
200    USB_HP_CAN_TX = 19,
201    ///20 - USB Low Priority or CAN RX0 interrupts
202    USB_LP_CAN_RX0 = 20,
203    ///21 - CAN RX1 interrupt
204    CAN_RX1 = 21,
205    ///22 - CAN SCE interrupt
206    CAN_SCE = 22,
207    ///23 - EXTI Line\[9:5\] interrupts
208    EXTI9_5 = 23,
209    ///24 - TIM1 Break interrupt
210    TIM1_BRK = 24,
211    ///25 - TIM1 Update interrupt
212    TIM1_UP = 25,
213    ///26 - TIM1 Trigger and Commutation interrupts
214    TIM1_TRG_COM = 26,
215    ///27 - TIM1 Capture Compare interrupt
216    TIM1_CC = 27,
217    ///28 - TIM2 global interrupt
218    TIM2 = 28,
219    ///29 - TIM3 global interrupt
220    TIM3 = 29,
221    ///30 - TIM4 global interrupt
222    TIM4 = 30,
223    ///31 - I2C1 event interrupt
224    I2C1_EV = 31,
225    ///32 - I2C1 error interrupt
226    I2C1_ER = 32,
227    ///33 - I2C2 event interrupt
228    I2C2_EV = 33,
229    ///34 - I2C2 error interrupt
230    I2C2_ER = 34,
231    ///35 - SPI1 global interrupt
232    SPI1 = 35,
233    ///36 - SPI2 global interrupt
234    SPI2 = 36,
235    ///37 - USART1 global interrupt
236    USART1 = 37,
237    ///38 - USART2 global interrupt
238    USART2 = 38,
239    ///39 - USART3 global interrupt
240    USART3 = 39,
241    ///40 - EXTI Line\[15:10\] interrupts
242    EXTI15_10 = 40,
243    ///41 - RTC Alarms through EXTI line interrupt
244    RTCALARM = 41,
245    ///43 - TIM8 Break interrupt
246    TIM8_BRK = 43,
247    ///44 - TIM8 Update interrupt
248    TIM8_UP = 44,
249    ///45 - TIM8 Trigger and Commutation interrupts
250    TIM8_TRG_COM = 45,
251    ///46 - TIM8 Capture Compare interrupt
252    TIM8_CC = 46,
253    ///47 - ADC3 global interrupt
254    ADC3 = 47,
255    ///48 - FSMC global interrupt
256    FSMC = 48,
257    ///49 - SDIO global interrupt
258    SDIO = 49,
259    ///50 - TIM5 global interrupt
260    TIM5 = 50,
261    ///51 - SPI3 global interrupt
262    SPI3 = 51,
263    ///52 - UART4 global interrupt
264    UART4 = 52,
265    ///53 - UART5 global interrupt
266    UART5 = 53,
267    ///54 - TIM6 global interrupt
268    TIM6 = 54,
269    ///55 - TIM7 global interrupt
270    TIM7 = 55,
271    ///56 - DMA2 Channel1 global interrupt
272    DMA2_CHANNEL1 = 56,
273    ///57 - DMA2 Channel2 global interrupt
274    DMA2_CHANNEL2 = 57,
275    ///58 - DMA2 Channel3 global interrupt
276    DMA2_CHANNEL3 = 58,
277    ///59 - DMA2 Channel4 and DMA2 Channel5 global interrupt
278    DMA2_CHANNEL4_5 = 59,
279}
280unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
281    #[inline(always)]
282    fn number(self) -> u16 {
283        self as u16
284    }
285}
286///Flexible static memory controller
287///
288///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#FSMC)
289pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
290impl core::fmt::Debug for FSMC {
291    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
292        f.debug_struct("FSMC").finish()
293    }
294}
295///Flexible static memory controller
296pub mod fsmc;
297///Power control
298///
299///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#PWR)
300pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
301impl core::fmt::Debug for PWR {
302    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
303        f.debug_struct("PWR").finish()
304    }
305}
306///Power control
307pub mod pwr;
308///Reset and clock control
309///
310///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RCC)
311pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
312impl core::fmt::Debug for RCC {
313    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
314        f.debug_struct("RCC").finish()
315    }
316}
317///Reset and clock control
318pub mod rcc;
319///General purpose I/O
320///
321///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA)
322pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
323impl core::fmt::Debug for GPIOA {
324    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
325        f.debug_struct("GPIOA").finish()
326    }
327}
328///General purpose I/O
329pub mod gpioa;
330///General purpose I/O
331///
332///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA)
333pub type GPIOB = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
334impl core::fmt::Debug for GPIOB {
335    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
336        f.debug_struct("GPIOB").finish()
337    }
338}
339///General purpose I/O
340pub use self::gpioa as gpiob;
341///General purpose I/O
342///
343///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA)
344pub type GPIOC = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
345impl core::fmt::Debug for GPIOC {
346    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
347        f.debug_struct("GPIOC").finish()
348    }
349}
350///General purpose I/O
351pub use self::gpioa as gpioc;
352///General purpose I/O
353///
354///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA)
355pub type GPIOD = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
356impl core::fmt::Debug for GPIOD {
357    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
358        f.debug_struct("GPIOD").finish()
359    }
360}
361///General purpose I/O
362pub use self::gpioa as gpiod;
363///General purpose I/O
364///
365///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA)
366pub type GPIOE = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
367impl core::fmt::Debug for GPIOE {
368    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
369        f.debug_struct("GPIOE").finish()
370    }
371}
372///General purpose I/O
373pub use self::gpioa as gpioe;
374///General purpose I/O
375///
376///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA)
377pub type GPIOF = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
378impl core::fmt::Debug for GPIOF {
379    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
380        f.debug_struct("GPIOF").finish()
381    }
382}
383///General purpose I/O
384pub use self::gpioa as gpiof;
385///General purpose I/O
386///
387///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#GPIOA)
388pub type GPIOG = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
389impl core::fmt::Debug for GPIOG {
390    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
391        f.debug_struct("GPIOG").finish()
392    }
393}
394///General purpose I/O
395pub use self::gpioa as gpiog;
396///Alternate function I/O
397///
398///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#AFIO)
399pub type AFIO = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
400impl core::fmt::Debug for AFIO {
401    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
402        f.debug_struct("AFIO").finish()
403    }
404}
405///Alternate function I/O
406pub mod afio;
407///EXTI
408///
409///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#EXTI)
410pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
411impl core::fmt::Debug for EXTI {
412    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
413        f.debug_struct("EXTI").finish()
414    }
415}
416///EXTI
417pub mod exti;
418///DMA controller
419///
420///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DMA1)
421pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
422impl core::fmt::Debug for DMA1 {
423    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
424        f.debug_struct("DMA1").finish()
425    }
426}
427///DMA controller
428pub mod dma1;
429///DMA controller
430///
431///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DMA1)
432pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
433impl core::fmt::Debug for DMA2 {
434    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
435        f.debug_struct("DMA2").finish()
436    }
437}
438///DMA controller
439pub use self::dma1 as dma2;
440///Secure digital input/output interface
441///
442///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#SDIO)
443pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_8000>;
444impl core::fmt::Debug for SDIO {
445    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
446        f.debug_struct("SDIO").finish()
447    }
448}
449///Secure digital input/output interface
450pub mod sdio;
451///Real time clock
452///
453///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#RTC)
454pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
455impl core::fmt::Debug for RTC {
456    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
457        f.debug_struct("RTC").finish()
458    }
459}
460///Real time clock
461pub mod rtc;
462///Backup registers
463///
464///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#BKP)
465pub type BKP = crate::Periph<bkp::RegisterBlock, 0x4000_6c04>;
466impl core::fmt::Debug for BKP {
467    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
468        f.debug_struct("BKP").finish()
469    }
470}
471///Backup registers
472pub mod bkp;
473///Independent watchdog
474///
475///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#IWDG)
476pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
477impl core::fmt::Debug for IWDG {
478    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
479        f.debug_struct("IWDG").finish()
480    }
481}
482///Independent watchdog
483pub mod iwdg;
484///Window watchdog
485///
486///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#WWDG)
487pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
488impl core::fmt::Debug for WWDG {
489    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
490        f.debug_struct("WWDG").finish()
491    }
492}
493///Window watchdog
494pub mod wwdg;
495///Advanced timer
496///
497///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM1)
498pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
499impl core::fmt::Debug for TIM1 {
500    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
501        f.debug_struct("TIM1").finish()
502    }
503}
504///Advanced timer
505pub mod tim1;
506///Advanced timer
507///
508///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM1)
509pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_3400>;
510impl core::fmt::Debug for TIM8 {
511    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
512        f.debug_struct("TIM8").finish()
513    }
514}
515///Advanced timer
516pub use self::tim1 as tim8;
517///General purpose timer
518///
519///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM2)
520pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
521impl core::fmt::Debug for TIM2 {
522    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
523        f.debug_struct("TIM2").finish()
524    }
525}
526///General purpose timer
527pub mod tim2;
528///General purpose timer
529///
530///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM2)
531pub type TIM3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
532impl core::fmt::Debug for TIM3 {
533    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
534        f.debug_struct("TIM3").finish()
535    }
536}
537///General purpose timer
538pub use self::tim2 as tim3;
539///General purpose timer
540///
541///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM2)
542pub type TIM4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
543impl core::fmt::Debug for TIM4 {
544    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
545        f.debug_struct("TIM4").finish()
546    }
547}
548///General purpose timer
549pub use self::tim2 as tim4;
550///General purpose timer
551///
552///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM2)
553pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
554impl core::fmt::Debug for TIM5 {
555    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
556        f.debug_struct("TIM5").finish()
557    }
558}
559///General purpose timer
560pub use self::tim2 as tim5;
561///General purpose timer
562///
563///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM9)
564pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4c00>;
565impl core::fmt::Debug for TIM9 {
566    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
567        f.debug_struct("TIM9").finish()
568    }
569}
570///General purpose timer
571pub mod tim9;
572///General purpose timer
573///
574///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM9)
575pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
576impl core::fmt::Debug for TIM12 {
577    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
578        f.debug_struct("TIM12").finish()
579    }
580}
581///General purpose timer
582pub use self::tim9 as tim12;
583///General purpose timer
584///
585///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM10)
586pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_5000>;
587impl core::fmt::Debug for TIM10 {
588    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
589        f.debug_struct("TIM10").finish()
590    }
591}
592///General purpose timer
593pub mod tim10;
594///General purpose timer
595///
596///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM10)
597pub type TIM11 = crate::Periph<tim10::RegisterBlock, 0x4001_5400>;
598impl core::fmt::Debug for TIM11 {
599    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
600        f.debug_struct("TIM11").finish()
601    }
602}
603///General purpose timer
604pub use self::tim10 as tim11;
605///General purpose timer
606///
607///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM10)
608pub type TIM13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
609impl core::fmt::Debug for TIM13 {
610    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
611        f.debug_struct("TIM13").finish()
612    }
613}
614///General purpose timer
615pub use self::tim10 as tim13;
616///General purpose timer
617///
618///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM10)
619pub type TIM14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
620impl core::fmt::Debug for TIM14 {
621    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
622        f.debug_struct("TIM14").finish()
623    }
624}
625///General purpose timer
626pub use self::tim10 as tim14;
627///Basic timer
628///
629///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM6)
630pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
631impl core::fmt::Debug for TIM6 {
632    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
633        f.debug_struct("TIM6").finish()
634    }
635}
636///Basic timer
637pub mod tim6;
638///Basic timer
639///
640///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM6)
641pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
642impl core::fmt::Debug for TIM7 {
643    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
644        f.debug_struct("TIM7").finish()
645    }
646}
647///Basic timer
648pub use self::tim6 as tim7;
649///Inter integrated circuit
650///
651///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1)
652pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
653impl core::fmt::Debug for I2C1 {
654    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
655        f.debug_struct("I2C1").finish()
656    }
657}
658///Inter integrated circuit
659pub mod i2c1;
660///Inter integrated circuit
661///
662///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1)
663pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
664impl core::fmt::Debug for I2C2 {
665    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
666        f.debug_struct("I2C2").finish()
667    }
668}
669///Inter integrated circuit
670pub use self::i2c1 as i2c2;
671///Serial peripheral interface
672///
673///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#SPI1)
674pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
675impl core::fmt::Debug for SPI1 {
676    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
677        f.debug_struct("SPI1").finish()
678    }
679}
680///Serial peripheral interface
681pub mod spi1;
682///Serial peripheral interface
683///
684///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#SPI1)
685pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
686impl core::fmt::Debug for SPI2 {
687    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
688        f.debug_struct("SPI2").finish()
689    }
690}
691///Serial peripheral interface
692pub use self::spi1 as spi2;
693///Serial peripheral interface
694///
695///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#SPI1)
696pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
697impl core::fmt::Debug for SPI3 {
698    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
699        f.debug_struct("SPI3").finish()
700    }
701}
702///Serial peripheral interface
703pub use self::spi1 as spi3;
704///Universal synchronous asynchronous receiver transmitter
705///
706///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USART1)
707pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
708impl core::fmt::Debug for USART1 {
709    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
710        f.debug_struct("USART1").finish()
711    }
712}
713///Universal synchronous asynchronous receiver transmitter
714pub mod usart1;
715///Universal synchronous asynchronous receiver transmitter
716///
717///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USART1)
718pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
719impl core::fmt::Debug for USART2 {
720    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
721        f.debug_struct("USART2").finish()
722    }
723}
724///Universal synchronous asynchronous receiver transmitter
725pub use self::usart1 as usart2;
726///Universal synchronous asynchronous receiver transmitter
727///
728///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USART1)
729pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
730impl core::fmt::Debug for USART3 {
731    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
732        f.debug_struct("USART3").finish()
733    }
734}
735///Universal synchronous asynchronous receiver transmitter
736pub use self::usart1 as usart3;
737///Analog to digital converter
738///
739///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#ADC1)
740pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
741impl core::fmt::Debug for ADC1 {
742    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
743        f.debug_struct("ADC1").finish()
744    }
745}
746///Analog to digital converter
747pub mod adc1;
748///Analog to digital converter
749///
750///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#ADC2)
751pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4001_2800>;
752impl core::fmt::Debug for ADC2 {
753    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
754        f.debug_struct("ADC2").finish()
755    }
756}
757///Analog to digital converter
758pub mod adc2;
759///Analog to digital converter
760///
761///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#ADC3)
762pub type ADC3 = crate::Periph<adc3::RegisterBlock, 0x4001_3c00>;
763impl core::fmt::Debug for ADC3 {
764    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
765        f.debug_struct("ADC3").finish()
766    }
767}
768///Analog to digital converter
769pub mod adc3;
770///Controller area network
771///
772///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#CAN)
773pub type CAN = crate::Periph<can::RegisterBlock, 0x4000_6400>;
774impl core::fmt::Debug for CAN {
775    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
776        f.debug_struct("CAN").finish()
777    }
778}
779///Controller area network
780pub mod can;
781///Digital to analog converter
782///
783///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DAC)
784pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
785impl core::fmt::Debug for DAC {
786    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
787        f.debug_struct("DAC").finish()
788    }
789}
790///Digital to analog converter
791pub mod dac;
792///Debug support
793///
794///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#DBGMCU)
795pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
796impl core::fmt::Debug for DBGMCU {
797    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
798        f.debug_struct("DBGMCU").finish()
799    }
800}
801///Debug support
802pub mod dbgmcu;
803///Universal asynchronous receiver transmitter
804///
805///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#UART4)
806pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
807impl core::fmt::Debug for UART4 {
808    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
809        f.debug_struct("UART4").finish()
810    }
811}
812///Universal asynchronous receiver transmitter
813pub mod uart4;
814///Universal asynchronous receiver transmitter
815///
816///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#UART4)
817pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
818impl core::fmt::Debug for UART5 {
819    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
820        f.debug_struct("UART5").finish()
821    }
822}
823///Universal asynchronous receiver transmitter
824pub use self::uart4 as uart5;
825///CRC calculation unit
826///
827///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#CRC)
828pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
829impl core::fmt::Debug for CRC {
830    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
831        f.debug_struct("CRC").finish()
832    }
833}
834///CRC calculation unit
835pub mod crc;
836///FLASH
837///
838///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#FLASH)
839pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
840impl core::fmt::Debug for FLASH {
841    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
842        f.debug_struct("FLASH").finish()
843    }
844}
845///FLASH
846pub mod flash;
847///Universal serial bus full-speed device interface
848///
849///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#USB)
850pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
851impl core::fmt::Debug for USB {
852    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
853        f.debug_struct("USB").finish()
854    }
855}
856///Universal serial bus full-speed device interface
857pub mod usb;
858///USB on the go full speed
859///
860///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#OTG_FS_DEVICE)
861pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
862impl core::fmt::Debug for OTG_FS_DEVICE {
863    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
864        f.debug_struct("OTG_FS_DEVICE").finish()
865    }
866}
867///USB on the go full speed
868pub mod otg_fs_device;
869///USB on the go full speed
870///
871///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#OTG_FS_GLOBAL)
872pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
873impl core::fmt::Debug for OTG_FS_GLOBAL {
874    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
875        f.debug_struct("OTG_FS_GLOBAL").finish()
876    }
877}
878///USB on the go full speed
879pub mod otg_fs_global;
880///USB on the go full speed
881///
882///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#OTG_FS_HOST)
883pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
884impl core::fmt::Debug for OTG_FS_HOST {
885    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
886        f.debug_struct("OTG_FS_HOST").finish()
887    }
888}
889///USB on the go full speed
890pub mod otg_fs_host;
891///USB on the go full speed
892///
893///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#OTG_FS_PWRCLK)
894pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
895impl core::fmt::Debug for OTG_FS_PWRCLK {
896    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
897        f.debug_struct("OTG_FS_PWRCLK").finish()
898    }
899}
900///USB on the go full speed
901pub mod otg_fs_pwrclk;
902///Ethernet: MAC management counters
903///
904///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#Ethernet_MMC)
905pub type ETHERNET_MMC = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
906impl core::fmt::Debug for ETHERNET_MMC {
907    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
908        f.debug_struct("ETHERNET_MMC").finish()
909    }
910}
911///Ethernet: MAC management counters
912pub mod ethernet_mmc;
913///Ethernet: media access control
914///
915///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#Ethernet_MAC)
916pub type ETHERNET_MAC = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
917impl core::fmt::Debug for ETHERNET_MAC {
918    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
919        f.debug_struct("ETHERNET_MAC").finish()
920    }
921}
922///Ethernet: media access control
923pub mod ethernet_mac;
924///Ethernet: Precision time protocol
925///
926///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#Ethernet_PTP)
927pub type ETHERNET_PTP = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
928impl core::fmt::Debug for ETHERNET_PTP {
929    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
930        f.debug_struct("ETHERNET_PTP").finish()
931    }
932}
933///Ethernet: Precision time protocol
934pub mod ethernet_ptp;
935///Ethernet: DMA controller operation
936///
937///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#Ethernet_DMA)
938pub type ETHERNET_DMA = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
939impl core::fmt::Debug for ETHERNET_DMA {
940    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
941        f.debug_struct("ETHERNET_DMA").finish()
942    }
943}
944///Ethernet: DMA controller operation
945pub mod ethernet_dma;
946///System control block ACTLR
947///
948///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#SCB_ACTRL)
949pub type SCB_ACTRL = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
950impl core::fmt::Debug for SCB_ACTRL {
951    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
952        f.debug_struct("SCB_ACTRL").finish()
953    }
954}
955///System control block ACTLR
956pub mod scb_actrl;
957///Nested vectored interrupt controller
958///
959///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#NVIC_STIR)
960pub type NVIC_STIR = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
961impl core::fmt::Debug for NVIC_STIR {
962    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
963        f.debug_struct("NVIC_STIR").finish()
964    }
965}
966///Nested vectored interrupt controller
967pub mod nvic_stir;
968///SysTick timer
969///
970///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#STK)
971pub type STK = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
972impl core::fmt::Debug for STK {
973    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
974        f.debug_struct("STK").finish()
975    }
976}
977///SysTick timer
978pub mod stk;
979#[no_mangle]
980static mut DEVICE_PERIPHERALS: bool = false;
981/// All the peripherals.
982#[allow(non_snake_case)]
983pub struct Peripherals {
984    ///FSMC
985    pub FSMC: FSMC,
986    ///PWR
987    pub PWR: PWR,
988    ///RCC
989    pub RCC: RCC,
990    ///GPIOA
991    pub GPIOA: GPIOA,
992    ///GPIOB
993    pub GPIOB: GPIOB,
994    ///GPIOC
995    pub GPIOC: GPIOC,
996    ///GPIOD
997    pub GPIOD: GPIOD,
998    ///GPIOE
999    pub GPIOE: GPIOE,
1000    ///GPIOF
1001    pub GPIOF: GPIOF,
1002    ///GPIOG
1003    pub GPIOG: GPIOG,
1004    ///AFIO
1005    pub AFIO: AFIO,
1006    ///EXTI
1007    pub EXTI: EXTI,
1008    ///DMA1
1009    pub DMA1: DMA1,
1010    ///DMA2
1011    pub DMA2: DMA2,
1012    ///SDIO
1013    pub SDIO: SDIO,
1014    ///RTC
1015    pub RTC: RTC,
1016    ///BKP
1017    pub BKP: BKP,
1018    ///IWDG
1019    pub IWDG: IWDG,
1020    ///WWDG
1021    pub WWDG: WWDG,
1022    ///TIM1
1023    pub TIM1: TIM1,
1024    ///TIM8
1025    pub TIM8: TIM8,
1026    ///TIM2
1027    pub TIM2: TIM2,
1028    ///TIM3
1029    pub TIM3: TIM3,
1030    ///TIM4
1031    pub TIM4: TIM4,
1032    ///TIM5
1033    pub TIM5: TIM5,
1034    ///TIM9
1035    pub TIM9: TIM9,
1036    ///TIM12
1037    pub TIM12: TIM12,
1038    ///TIM10
1039    pub TIM10: TIM10,
1040    ///TIM11
1041    pub TIM11: TIM11,
1042    ///TIM13
1043    pub TIM13: TIM13,
1044    ///TIM14
1045    pub TIM14: TIM14,
1046    ///TIM6
1047    pub TIM6: TIM6,
1048    ///TIM7
1049    pub TIM7: TIM7,
1050    ///I2C1
1051    pub I2C1: I2C1,
1052    ///I2C2
1053    pub I2C2: I2C2,
1054    ///SPI1
1055    pub SPI1: SPI1,
1056    ///SPI2
1057    pub SPI2: SPI2,
1058    ///SPI3
1059    pub SPI3: SPI3,
1060    ///USART1
1061    pub USART1: USART1,
1062    ///USART2
1063    pub USART2: USART2,
1064    ///USART3
1065    pub USART3: USART3,
1066    ///ADC1
1067    pub ADC1: ADC1,
1068    ///ADC2
1069    pub ADC2: ADC2,
1070    ///ADC3
1071    pub ADC3: ADC3,
1072    ///CAN
1073    pub CAN: CAN,
1074    ///DAC
1075    pub DAC: DAC,
1076    ///DBGMCU
1077    pub DBGMCU: DBGMCU,
1078    ///UART4
1079    pub UART4: UART4,
1080    ///UART5
1081    pub UART5: UART5,
1082    ///CRC
1083    pub CRC: CRC,
1084    ///FLASH
1085    pub FLASH: FLASH,
1086    ///USB
1087    pub USB: USB,
1088    ///OTG_FS_DEVICE
1089    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1090    ///OTG_FS_GLOBAL
1091    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1092    ///OTG_FS_HOST
1093    pub OTG_FS_HOST: OTG_FS_HOST,
1094    ///OTG_FS_PWRCLK
1095    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1096    ///Ethernet_MMC
1097    pub ETHERNET_MMC: ETHERNET_MMC,
1098    ///Ethernet_MAC
1099    pub ETHERNET_MAC: ETHERNET_MAC,
1100    ///Ethernet_PTP
1101    pub ETHERNET_PTP: ETHERNET_PTP,
1102    ///Ethernet_DMA
1103    pub ETHERNET_DMA: ETHERNET_DMA,
1104    ///SCB_ACTRL
1105    pub SCB_ACTRL: SCB_ACTRL,
1106    ///NVIC_STIR
1107    pub NVIC_STIR: NVIC_STIR,
1108    ///STK
1109    pub STK: STK,
1110}
1111impl Peripherals {
1112    /// Returns all the peripherals *once*.
1113    #[cfg(feature = "critical-section")]
1114    #[inline]
1115    pub fn take() -> Option<Self> {
1116        critical_section::with(|_| {
1117            if unsafe { DEVICE_PERIPHERALS } {
1118                return None;
1119            }
1120            Some(unsafe { Peripherals::steal() })
1121        })
1122    }
1123    /// Unchecked version of `Peripherals::take`.
1124    ///
1125    /// # Safety
1126    ///
1127    /// Each of the returned peripherals must be used at most once.
1128    #[inline]
1129    pub unsafe fn steal() -> Self {
1130        DEVICE_PERIPHERALS = true;
1131        Peripherals {
1132            FSMC: FSMC::steal(),
1133            PWR: PWR::steal(),
1134            RCC: RCC::steal(),
1135            GPIOA: GPIOA::steal(),
1136            GPIOB: GPIOB::steal(),
1137            GPIOC: GPIOC::steal(),
1138            GPIOD: GPIOD::steal(),
1139            GPIOE: GPIOE::steal(),
1140            GPIOF: GPIOF::steal(),
1141            GPIOG: GPIOG::steal(),
1142            AFIO: AFIO::steal(),
1143            EXTI: EXTI::steal(),
1144            DMA1: DMA1::steal(),
1145            DMA2: DMA2::steal(),
1146            SDIO: SDIO::steal(),
1147            RTC: RTC::steal(),
1148            BKP: BKP::steal(),
1149            IWDG: IWDG::steal(),
1150            WWDG: WWDG::steal(),
1151            TIM1: TIM1::steal(),
1152            TIM8: TIM8::steal(),
1153            TIM2: TIM2::steal(),
1154            TIM3: TIM3::steal(),
1155            TIM4: TIM4::steal(),
1156            TIM5: TIM5::steal(),
1157            TIM9: TIM9::steal(),
1158            TIM12: TIM12::steal(),
1159            TIM10: TIM10::steal(),
1160            TIM11: TIM11::steal(),
1161            TIM13: TIM13::steal(),
1162            TIM14: TIM14::steal(),
1163            TIM6: TIM6::steal(),
1164            TIM7: TIM7::steal(),
1165            I2C1: I2C1::steal(),
1166            I2C2: I2C2::steal(),
1167            SPI1: SPI1::steal(),
1168            SPI2: SPI2::steal(),
1169            SPI3: SPI3::steal(),
1170            USART1: USART1::steal(),
1171            USART2: USART2::steal(),
1172            USART3: USART3::steal(),
1173            ADC1: ADC1::steal(),
1174            ADC2: ADC2::steal(),
1175            ADC3: ADC3::steal(),
1176            CAN: CAN::steal(),
1177            DAC: DAC::steal(),
1178            DBGMCU: DBGMCU::steal(),
1179            UART4: UART4::steal(),
1180            UART5: UART5::steal(),
1181            CRC: CRC::steal(),
1182            FLASH: FLASH::steal(),
1183            USB: USB::steal(),
1184            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1185            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1186            OTG_FS_HOST: OTG_FS_HOST::steal(),
1187            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1188            ETHERNET_MMC: ETHERNET_MMC::steal(),
1189            ETHERNET_MAC: ETHERNET_MAC::steal(),
1190            ETHERNET_PTP: ETHERNET_PTP::steal(),
1191            ETHERNET_DMA: ETHERNET_DMA::steal(),
1192            SCB_ACTRL: SCB_ACTRL::steal(),
1193            NVIC_STIR: NVIC_STIR::steal(),
1194            STK: STK::steal(),
1195        }
1196    }
1197}
stm32f1_staging/stm32f103/mod.rs

stm32f1_staging/stm32f103/
mod.rs
